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74AC109LCTR PDF预览

74AC109LCTR

更新时间: 2024-01-04 00:41:00
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
12页 339K
描述
J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CQCC20, CERAMIC, LCC-20

74AC109LCTR 技术参数

生命周期:Transferred包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
系列:ACJESD-30 代码:R-PDSO-G16
长度:10.11 mm负载电容(CL):50 pF
逻辑集成电路类型:J-KBAR FLIP-FLOP位数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):10.5 ns
认证状态:Not Qualified座面最大高度:2.108 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:125 MHz
Base Number Matches:1

74AC109LCTR 数据手册

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March 2007  
74AC109, 74ACT109  
tm  
Dual JK Positive Edge-Triggered Flip-Flop  
Features  
General Description  
I reduced by 50%  
The AC/ACT109 consists of two high-speed completely  
independent transition clocked JK flip-flops. The clocking  
operation is independent of rise and fall times of the  
clock waveform. The JK design allows operation as a  
D-Type flip-flop (refer to AC/ACT74 data sheet) by  
connecting the J and K inputs together.  
CC  
Outputs source/sink 24mA  
ACT109 has TTL-compatible inputs  
Asynchronous Inputs:  
– LOW input to S (Set) sets Q to HIGH level  
D
– LOW input to C (Clear) sets Q to LOW level  
D
– Clear and Set are independent of clock  
– Simultaneous LOW on C and S makes both  
D
D
Q and Q HIGH  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
74AC109SC  
74AC109SJ  
74AC109MTC  
M16A  
M16D  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MTC16  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74ACT109SC  
74AC109MTC  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
MTC16  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74ACT109PC  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
J , J , K , K  
2
Data Inputs  
1
2
1
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
2
C
, C  
D2  
D1  
S
, S  
D2  
D1  
Q , Q , Q , Q  
2
1
2
1
FACT™ is a trademark of Fairchild Semiconductor Corporation.  
©1988 Fairchild Semiconductor Corporation  
74AC109, 74ACT109 Rev. 1.5  
www.fairchildsemi.com  

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