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74ABT377 PDF预览

74ABT377

更新时间: 2024-02-13 00:50:44
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器时钟
页数 文件大小 规格书
9页 104K
描述
Octal D-Type Flip-Flop with Clock Enable

74ABT377 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.38Is Samacsys:N
其他特性:WITH HOLD MODE系列:ABT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH最大电源电流(ICC):30 mA
传播延迟(tpd):4.9 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:250 MHz
Base Number Matches:1

74ABT377 数据手册

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January 1993  
Revised November 1999  
74ABT377  
Octal D-Type Flip-Flop with Clock Enable  
General Description  
Features  
The ABT377 has eight edge-triggered, D-type flip-flops  
with individual D inputs and Q outputs. The common buff-  
ered Clock (CP) input loads all flip-flops simultaneously  
when the Clock Enable (CE) is LOW.  
Clock enable for address and data synchronization  
applications  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
The CE input must be stable only one setup time prior to  
the LOW-to-HIGH clock transition for predictable operation.  
See ABT273 for master reset version  
See ABT373 for transparent latch version  
See ABT374 for 3-STATE version  
Output sink capability of 64 mA, source capability  
of 32 mA  
Guaranteed latchup protection  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Non-destructive hot insertion capability  
Disable time less than enable time to avoid bus  
contention  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT377CSC  
74ABT377CSJ  
74ABT377CMSA  
74ABT377CMTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MSA20  
MTC20  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Descriptions  
Data Inputs  
D0D7  
Clock Enable (Active LOW)  
Clock Pulse Input  
CE  
CP  
Q0Q7  
Data Outputs  
Truth Table  
Operating Mode  
Inputs  
Output  
Qn  
CP  
Dn  
CE  
I
Load 1”  
Load 0”  
Hold  
h
I
H
I
L
h
X
X
No Change  
No Change  
(Do Nothing)  
X
H
H
X
h
= HIGH Voltage Level  
= Immaterial  
= HIGH Voltage Level one setup time prior to the  
LOW-to-HIGH Clock Transition  
L = LOW Voltage Level  
= LOW-to-HIGH Clock Transition  
I
= LOW Voltage Level one setup time prior to the  
LOW-to-HIGH Clock Transition  
© 1999 Fairchild Semiconductor Corporation  
DS011550  
www.fairchildsemi.com  

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