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74ABT273CSJX PDF预览

74ABT273CSJX

更新时间: 2024-02-14 22:41:52
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
9页 101K
描述
Octal D-Type Flip-Flop

74ABT273CSJX 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.15系列:ABT
JESD-30 代码:R-PDIP-T20长度:26.695 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
最大电源电流(ICC):30 mA传播延迟(tpd):7.3 ns
认证状态:Not Qualified座面最大高度:4.06 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:BICMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:150 MHz
Base Number Matches:1

74ABT273CSJX 数据手册

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January 1993  
Revised November 1999  
74ABT273  
Octal D-Type Flip-Flop  
General Description  
Features  
The ABT273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
Buffered, asynchronous Master Reset  
See ABT377 for clock enable version  
See ABT373 for transparent latch version  
See ABT374 for 3-STATE version  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
Output sink capability of 64 mA, source capability of  
32 mA  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
Guaranteed latchup protection  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Non-destructive hot insertion capability  
Disable time less than enable time to avoid bus conten-  
tion  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT273CSC  
74ABT273CSJ  
74ABT273CMSA  
74ABT273CMTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MSA20  
MTC20  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D0D7  
MR  
Description  
Data Inputs  
Master Reset (Active LOW)  
Clock Pulse Input (Active Rising Edge)  
Data Outputs  
CP  
Q0Q7  
© 1999 Fairchild Semiconductor Corporation  
DS011549  
www.fairchildsemi.com  

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