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100351SC PDF预览

100351SC

更新时间: 2024-02-20 10:21:52
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 96K
描述
Low Power Hex D-Type Flip-Flop

100351SC 技术参数

生命周期:Contact Manufacturer包装说明:QFF,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.59其他特性:WITH DUAL CLOCK
系列:100KJESD-30 代码:S-GQFP-F24
长度:9.398 mm逻辑集成电路类型:D FLIP-FLOP
位数:6功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:QFF封装形状:SQUARE
封装形式:FLATPACK传播延迟(tpd):2.2 ns
筛选级别:MIL-STD-883 Class B座面最大高度:2.159 mm
表面贴装:YES技术:ECL
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:9.398 mm
最小 fmax:375 MHzBase Number Matches:1

100351SC 数据手册

 浏览型号100351SC的Datasheet PDF文件第2页浏览型号100351SC的Datasheet PDF文件第3页浏览型号100351SC的Datasheet PDF文件第4页浏览型号100351SC的Datasheet PDF文件第5页浏览型号100351SC的Datasheet PDF文件第6页浏览型号100351SC的Datasheet PDF文件第7页 
July 1988  
Revised August 2000  
100351  
Low Power Hex D-Type Flip-Flop  
General Description  
The 100351 contains six D-type edge-triggered, master/  
slave flip-flops with true and complement outputs, a pair of  
common Clock inputs (CPa and CPb) and common Master  
Features  
40% power reduction of the 100151  
2000V ESD protection  
Pin/function compatible with 100151  
Voltage compensated operating range:  
4.2V to 5.7V  
Reset (MR) input. Data enters a master when both CPa  
and CPb are LOW and transfers to the slave when CPa and  
CPb (or both) go HIGH. The MR input overrides all other  
Available to industrial grade temperature range  
inputs and makes the Q outputs LOW. All inputs have  
50 kpull-down resistors.  
Ordering Code:  
Order Number Package Number  
Package Description  
100351SC  
100351PC  
100351QC  
100351QI  
M24B  
N24E  
V28A  
V28A  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
Industrial Temperature Range (40°C to +85°C)  
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagrams  
24-Pin DIP/SOIC  
28-Pin PLCC  
Pin Descriptions  
Pin Names  
Description  
D0D5  
CPa, CPb  
MR  
Data Inputs  
Common Clock Inputs  
Asynchronous Master Reset Input  
Data Outputs  
Q0Q5  
Q0Q5  
Complementary Data Outputs  
© 2000 Fairchild Semiconductor Corporation  
DS009885  
www.fairchildsemi.com  

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