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100302 PDF预览

100302

更新时间: 2024-01-15 00:27:01
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
8页 81K
描述
Low Power Quint 2-Input OR/NOR Gate

100302 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QFF, QFL24,.4SQReach Compliance Code:unknown
风险等级:5.85Is Samacsys:N
JESD-30 代码:S-XQFP-F24JESD-609代码:e0
逻辑集成电路类型:OR/NOR GATE端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:QFF
封装等效代码:QFL24,.4SQ封装形状:SQUARE
封装形式:FLATPACK电源:-4.5 V
最大电源电流(ICC):48 mAProp。Delay @ Nom-Sup:1.7 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:38535V;38534K;883S子类别:Gates
表面贴装:YES技术:ECL100K
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

100302 数据手册

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August 1989  
Revised August 2000  
100302  
Low Power Quint 2-Input OR/NOR Gate  
General Description  
The 100302 is a monolithic quint 2-input OR/NOR gate with  
common enable. All inputs have 50 kpull-down resistors  
and all outputs are buffered.  
Features  
43% power reduction of the 100102  
2000V ESD protection  
Pin/function compatible with 100102  
Voltage compensated operating range = −4.2V to 5.7V  
Available to industrial grade temperature range  
(PLCC package only)  
Ordering Code:  
Order Number Package Number  
Package Description  
100302SC  
100302PC  
100302QC  
100302QI  
M24B  
N24E  
V28A  
V28A  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
Industrial Temperature Range (40°C to +85°C)  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
24-Pin DIP/SOIC  
28-Pin PLCC  
Pin Descriptions  
Pin Names  
naDne  
Description  
D
Data Inputs  
Enable Input  
Data Outputs  
E
OaOe  
OaOe  
Complementary Data Outputs  
© 2000 Fairchild Semiconductor Corporation  
DS010580  
www.fairchildsemi.com  

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