Datasheet > F59L4G81XB-25BG2X

F59L4G81XB-25BG2X

更新时间： 2024-01-06 01:08:08

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
87页	2290K
描述
4 Gbit (512M x 8) 3.3V NAND Flash Memory

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数据手册

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ESMT

F59L4G81XB (2X)

Flash

4 Gbit (512M x 8)

3.3V NAND Flash Memory

FEATURES



Operating voltage range

V_CC: 2.7–3.6V

Open NAND Flash Interface (ONFI) 1.0-compliant1

Single-level cell (SLC) technology

Organization



Operation status byte provides software method for

detecting



Operation completion

Pass/Fail condition

Write-protect status

Page size: 4352 bytes (4096 + 256 bytes)

Block size: 64 pages

Number of planes: 1

Ready/Busy# (R/B#) signal provides a hardware method

of detecting operation completion

WP# signal: Write protect entire device

ECC: 8-bit internal ECC is disabled at default2. It can be

toggled using the SET FEATURE command

Blocks 0 is valid when shipped from factory with ECC. For

minimum required ECC, see Error Management.

RESET (FFh) required as first command after power- on.

Internal data move operations supported within the plane

from which data is read



Asynchronous I/O performance

^tRC/^tWC: 25ns

Array performance



Read page: 115μs (MAX) with on-die ECC enabled

Read page: 25μs (MAX) with on-die ECC disabled

Program page: 200μs (TYP) with on-die ECC

disabled



Quality and reliability

Program page: 240μs (TYP) with on-die ECC enabled

Erase block: 2ms (TYP)

Endurance: 100,000 PROGRAM/ERASE cycles

Data retention: JESD47G-compliant; see qualification

report



Command set: ONFI NAND Flash protocol

Advanced command set

Additional: Uncycled data retention: 10 years 24/7 @

70°C

Program page cache mode

Read page cache mode

Permanent block locking (blocks 47:0)

One-time programmable (OTP) mode

Block lock

Programmable drive strength

Read unique ID

Internal data move

ORDERING INFORMATION

Product ID

Speed

25 ns

Package

Comments

Pb-free

F59L4G81XB -25TG2X

F59L4G81XB -25BG2X

F59L4G81XB -25BCG2X

48 pin TSOPI

63 ball BGA

67 ball BGA

Pb-free

GENERAL DESCRIPTION

NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly

multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the

asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device

status (R/B#).

This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another,

enabling future upgrades to higher densities with no board redesign.

A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. An NAND Flash die is

the minimum unit that can independently execute commands and report status. An NAND Flash die, in the ONFI specification, is

referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and

Array Organization.

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2019

Revision: 1.0 1/87

12 3 4 5 6 7...87

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与F59L4G81XB-25BG2X相关器件

型号	品牌	获取价格	描述	数据表
F59L4G81XB-25TG2X	ESMT	获取价格	4 Gbit (512M x 8) 3.3V NAND Flash Memory
F59L8G81XSB	ESMT	获取价格	8 Gbit (1Gb x 8) 3.3V NAND Flash Memory
F59L8G81XSB-25BG2X	ESMT	获取价格	8 Gbit (1Gb x 8) 3.3V NAND Flash Memory
F59L8G81XSB-25TG2X	ESMT	获取价格	8 Gbit (1Gb x 8) 3.3V NAND Flash Memory
F5A3	EDAL	获取价格	Silicon Power Rectifiers
F5AAG	GOOD-ARK	获取价格
F5B3	EDAL	获取价格	Silicon Power Rectifiers
F5BA722M5M6UW-J	TAIYO YUDEN	获取价格	SAW Filter, 1 Function(s), 722.5MHz,
F5C	ETC	获取价格	Peripheral IC
F5C2	ETC	获取价格	Peripheral IC

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