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F59L2G81LA-25BG PDF预览

F59L2G81LA-25BG

更新时间： 2024-11-15 02:52:11
品牌 Logo 应用领域
晶豪 - ESMT /
页数 文件大小 规格书
55页 1742K
描述
2 Gbit (256M x 8) 3.3V NAND Flash Memory

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F59L2G81LA-25BG 数据手册

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ESMT  
F59L2G81LA  
2 Gbit (256M x 8)  
3.3V NAND Flash Memory  
Flash  
FEATURES  
ꢀ
ꢀ
Voltage Supply: 3.3V (2.7V ~ 3.6V)  
Organization  
- Memory Cell Array: (256M + 16M) x 8bit  
- Data Register: (2K + 64) x 8bit  
ꢀ
Reliable CMOS Floating Gate Technology  
- ECC Requirement: 1bit/528Byte  
- Endurance: 100K Program/Erase cycles  
- Data Retention: 10 years  
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ꢀ
Command Register Operation  
Automatic Page 0 Read at Power-Up Option  
- Boot from NAND support  
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ꢀ
Automatic Program and Erase  
- Page Program: (2K + 64) byte  
- Block Erase: (128K + 4K) byte  
- Automatic Memory Download  
Page Read Operation  
- Page Size: (2K + 64) bytes  
- Random Read: 25us (Max.)  
- Serial Access: 25ns (Min.)  
Memory Cell: 1bit/Memory Cell  
Fast Write Cycle Time  
- Program time: 400us (Typ.)  
- Block Erase time: 3ms (Typ.)  
Command/Address/Data Multiplexed I/O Port  
ꢀ
ꢀ
ꢀ
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NOP: 4 cycles  
Cache Program Operation for High Performance Program  
Cache Read Operation  
Copy-Back Operation  
- EDO mode  
- OTP Operation  
- Two-Plane Operation  
Bad-Block-Protect  
ꢀ
ꢀ
ꢀ
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Hardware Data Protection  
- Program/Erase Lockout During Power Transitions  
ORDERING INFORMATION  
Product ID  
Speed  
25 ns  
25 ns  
Package  
48 pin TSOPI  
63 ball BGA  
Comments  
Pb-free  
F59L2G81LA-25TG  
F59L2G81LA-25BG  
Pb-free  
GENERAL DESCRIPTION  
The device is a 256Mx8bit with spare 16Mx8bit capacity. The  
device is offered in 3.3V VCC Power Supply. Its NAND cell  
provides the most cost-effective solution for the solid state mass  
storage market. The memory is divided into blocks that can be  
erased independently so it is possible to preserve valid data  
while old data is erased.  
inputs as well as data input/output. The copy back function  
allows the optimization of defective blocks management: when a  
page program operation fails the data can be directly  
programmed in another page inside the same array section  
without the time consuming serial data insertion phase. The  
cache program feature allows the data insertion in the cache  
register while the data register is copied into the Flash array.  
This pipelined program operation improves the program  
throughput when long files are written inside the memory. A  
cache read feature is also implemented. This feature allows to  
dramatically improving the read throughput when consecutive  
pages have to be streamed out. This device includes extra  
feature: Automatic Read at Power Up.  
The device contains 2048 blocks, composed by 64 pages  
consisting in two NAND structures of 32 series connected Flash  
cells. A program operation allows to write the 2112-Word page in  
typical 400us and an erase operation can be performed in typical  
3ms on a 128K-Byte for X8 device block.  
Data in the page mode can be read out at 25ns cycle time per  
Word. The I/O pins serve as the ports for address and command  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2016  
Revision: 1.0  
1/55  
1234567...55

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