Datasheet > F50L4G41XB

F50L4G41XB

更新时间： 2024-01-05 15:13:05

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
51页	1471K
描述
3.3V 4 Gbit SPI-NAND Flash Memory

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中文翻译

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数据手册

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F50L4G41XB 数据手册

ESMT

F50L4G41XB (2X)

3.3V 4 Gbit

SPI-NAND Flash Memory

Flash

FEATURES



Single-level cell (SLC) technology

Organization



Security

- Block 0 is valid when shipped from factory with ECC

enabled

- Software write protection with lock register

- Hardware write protection to freeze BP bits

- Lock tight to freeze BP bits during one power cycle

- Permanent block lock protection

- OTP Space: 10 pages one-time programmable NAND

Flash memory area

Quality and reliability

- Endurance: 100,000 PROGRAM/ERASE cycles

- Data retention: JESD47H-compliant; see qualification

report

- Additional: Uncycled data retention: 10 years 24/7 @ 70°C

Operating voltage range

- V_CC= 2.7–3.6V

- Page size ×1: 4352 bytes (4096 + 256 bytes)

- Block size: 64 pages (256K + 16K bytes)

- Plane size: 1 × 2048 blocks

Standard and extended SPI-compatible serial bus interface

- Instruction, address on 1 pin; data out on 1, 2, or 4 pins

- Instruction on 1 pin; address, data out on 2 or 4 pins

- Instruction, address on 1 pin; data in on 1 or 4 pins

- Continuous read within block, boot up ready, or

configure-able by feature register

User-selectable internal ECC supported

- 8 bits/sector

Array performance

- 133 MHz clock frequency (MAX)

- Page read: 25μs (MAX) with on-die ECC disabled; 115μs

(MAX) with on-die ECC enabled

- Page program: 200μs (TYP) with on-die ECC disabled;

240μs (TYP) with on-die ECC enabled

- Block erase: 2ms (TYP)



Operating temperature

- Commercial: 0°C to +70°C



Advanced features

- Read page cache mode (x2, x4, Dual, Quad, and Random)

- Read unique ID

- Read parameter page

Device initialization

- Automatic device initialization after power-up

ORDERING INFORMATION

Product ID

Speed

Package

8-contact LGA

Comments

F50L4G41XB-104RAG2X

104MHz

133MHz

8x6mm

Pb-free

F50L4G41XB-133RAG2X

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2019

Revision: 1.0 1/51

12 3 4 5 6 7...51

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