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F49L800UA-90TIG PDF预览

F49L800UA-90TIG

更新时间： 2024-01-07 03:28:04
品牌 Logo 应用领域
晶豪 - ESMT 闪存
页数 文件大小 规格书
47页 468K
描述
8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory

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F49L800UA-90TIG 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
零件包装代码：TSOP1包装说明：TSOP1, TSSOP48,.8,20
针数：48Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.68最长访问时间：90 ns
备用内存宽度：8启动块：TOP
命令用户界面：YES数据轮询：YES
耐久性：100000 Write/Erase CyclesJESD-30 代码：R-PDSO-G48
长度：18.4 mm内存密度：8388608 bit
内存集成电路类型：FLASH内存宽度：16
功能数量：1部门数/规模：1,2,1,15
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1封装等效代码：TSSOP48,.8,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/3.3 V编程电压：3 V
认证状态：Not Qualified就绪/忙碌：YES
座面最大高度：1.2 mm部门规模：16K,8K,32K,64K
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.05 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED切换位：YES
类型：NOR TYPE宽度：12 mm

F49L800UA-90TIG 数据手册

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ESMT  
F49L800UA/F49L800BA  
Operation Temperature Condition -40°C~85°C  
8 Mbit (1M x 8/512K x 16)  
3V Only CMOS Flash Memory  
1. FEATURES  
z
Single supply voltage 2.7V-3.6V  
Fast access time: 70/90 ns  
z
Ready/Busy (RY/BY )  
z
- RY/  
output pin for detection of program or erase  
BY  
operation completion  
End of program or erase detection  
- Data polling  
- Toggle bits  
Hardware reset  
z
z
1,048,576x8 / 524,288x16 switchable by BYTE pin  
Compatible with JEDEC standard  
- Pin-out, packages and software commands  
compatible with single-power supply Flash  
Low power consumption  
- 7mA typical active current  
- 25uA typical standby current  
100,000 program/erase cycles typically  
20 years data retention  
Command register architecture  
z
z
z
z
- Hardware pin(  
RESET  
to the read mode  
) resets the internal state machine  
z
z
z
Sector Protection /Unprotection  
- Hardware Protect/Unprotect any combination of sectors  
from a program or erase operation.  
Low VCC Write inhibit is equal to or less than 2.0V  
Boot Sector Architecture  
z
z
- Byte programming (9us typical)  
- Sector Erase(sector structure: one 16 KB, two 8 KB,  
one 32 KB, and fifteen 64 KB)  
- U = Upper Boot Block  
z
Auto Erase (chip & sector) and Auto Program  
- Any combination of sectors can be erased  
concurrently; Chip erase also provided.  
- Automatically program and verify data at specified  
address  
- B = Bottom Boot Block  
Packages available:  
- 48-pin TSOPI  
- All Pb-free products are RoHS-Compliant  
z
z
Erase Suspend/Erase Resume  
- Suspend or Resume erasing sectors to allow the  
read/program in another sector  
2. ORDERING INFORMATION  
Part No  
Boot  
Speed Package Comments  
Part No  
Boot Speed Package Comments  
F49L800UA-70TIG Upper  
F49L800BA-70TIG Bottom  
70 ns  
70 ns  
TSOPI  
TSOPI  
Pb-free  
Pb-free  
F49L800UA-90TIG Upper 90 ns  
F49L800BA-90TIG Bottom 90 ns  
TSOPI  
TSOPI  
Pb-free  
Pb-free  
3. GENERAL DESCRIPTION  
The F49L800UA/F49L800BA is a 8 Megabit, 3V only  
CMOS Flash memory device organized as 1M bytes of 8  
bits or 512K words of 16bits. This device is packaged in  
standard 48-pin TSOP. It is designed to be programmed  
and erased both in system and can in standard EPROM  
programmers.  
The F49L800UA/F49L800BA features a sector erase  
architecture. The device memory array is divided into one  
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64  
Kbytes. Sectors can be erased individually or in groups  
without affecting the data in other sectors. Multiple-sector  
erase and whole chip erase capabilities provide the  
flexibility to revise the data in the device.  
With access times of 70 ns and 90 ns, the  
F49L800UA/F49L800BA allows the operation of  
high-speed microprocessors. The device has separate  
The sector protect/unprotect feature disables both  
program and erase operations in any combination of the  
sectors of the memory. This can be achieved in-system or  
via programming equipment.  
chip enable  
, write enable  
, and output enable  
WE  
OE  
CE  
controls. ESMT's memory devices reliably store memory  
data even after 100,000 program and erase cycles.  
A low VCC detector inhibits write operations on loss of  
power. End of program or erase is detected by the  
Ready/Busy status pin, Data Polling of DQ7, or by the  
Toggle Bit I feature on DQ6. Once the program or erase  
cycle has been successfully completed, the device  
internally resets to the Read mode.  
The F49L800UA/F49L800BA is entirely pin and  
command set compatible with the JEDEC standard for 8  
Megabit Flash memory devices. Commands are written to  
the command register using standard microprocessor  
write timings.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jan. 2008  
Revision: 1.2  
1/47  
1234567...47

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