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F49L004BA-90NP PDF预览

F49L004BA-90NP

更新时间： 2024-11-27 19:55:23
品牌 Logo 应用领域
晶豪 - ESMT /
页数 文件大小 规格书
46页 588K
描述
Flash Memory,

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中文翻译

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F49L004BA-90NP 技术参数

生命周期：Contact Manufacturer包装说明：,
Reach Compliance Code：unknown风险等级：5.8
Base Number Matches：1

F49L004BA-90NP 数据手册

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EFST  
F49L004UA / F49L004BA  
4 Mbit (512K x 8)  
3V Only CMOS Flash Memory  
1. FEATURES  
z
z
z
Single supply voltage 2.7V-3.6V  
Fast access time: 70/90 ns  
Compatible with JEDEC standard  
- Pinout, packages and software commands  
compatible with single-power supply Flash  
Low power consumption  
z
Ready/Busy (RY/  
)
BY  
- RY/  
output pin for detection of program or erase  
BY  
operation completion  
End of program or erase detection  
- Data polling  
z
z
- Toggle bits  
- 20mA typical active current  
- 0.2uA typical standby current  
z
z
Hardware reset  
- Hardware pin(  
RESET  
to the read mode  
Sector Protection /Unprotection  
- Hardware Protect/Unprotect any combination of sectors  
from a program or erase operation.  
Low VCC Write inhibit is equal to or less than 2.0V  
Boot Sector Architecture  
- U = Upper Boot Sector  
- B = Bottom Boot Sector  
Packages available:  
- 40-pin TSOPI  
) resets the internal state machine  
z
z
100,000 program/erase cycles typically  
Command register architecture  
- Byte programming (9us typical)  
- Sector Erase(sector structure: one 16 KB, two 8 KB,  
one 32 KB, and seven 64 KB)  
Auto Erase (chip & sector) and Auto Program  
- Any combination of sectors can be erased  
concurrently; Chip erase also provided.  
- Automatically program and verify data at specified  
address  
z
z
z
z
z
Erase Suspend/Erase Resume  
- Suspend or Resume erasing sectors to allow the  
read/program in another sector  
- 32-pin PLCC  
2. ORDERING INFORMATION  
Part No  
Boot  
Speed  
Package  
Part No  
Boot  
Speed  
Package  
F49L004UA-70T  
F49L004UA-70N  
F49L004BA-70T  
F49L004BA-70N  
Upper  
Upper  
70 ns  
70 ns  
70 ns  
70 ns  
TSOPI  
PLCC  
TSOPI  
PLCC  
F49L004UA-90 T  
F49L004UA-90N  
F49L004BA-90T  
F49L004BA-90N  
Upper  
Upper  
90 ns  
90 ns  
90 ns  
90 ns  
TSOPI  
PLCC  
TSOPI  
PLCC  
Bottom  
Bottom  
Bottom  
Bottom  
3. GENERAL DESCRIPTION  
The F49L004UA/ F49L004BA is a 4 Megabit, 3V only  
CMOS Flash memory device organized as 512K bytes of  
8 bits. This device is packaged in standard 40-pin TSOP  
and 32-pin PLCC. It is designed to be programmed and  
erased both in system and can in standard EPROM  
programmers.  
The F49L004UA/ F49L004BA features a sector erase  
architecture. The device memory array is divided into one  
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64  
Kbytes. Sectors can be erased individually or in groups  
without affecting the data in other sectors. Multiple-sector  
erase and whole chip erase capabilities provide the  
flexibility to revise the data in the device.  
With access times of 70 ns and 90 ns, the F49L004UA/  
F49L004BA allows the operation of high-speed  
microprocessors. The device has separate chip enable  
The sector protect/unprotect feature disables both  
program and erase operations in any combination of the  
sectors of the memory. This can be achieved in-system or  
via programming equipment.  
, write enable  
, and output enable  
controls.  
OE  
WE  
CE  
EFST's memory devices reliably store memory data even  
after 100,000 program and erase cycles.  
A low VCC detector inhibits write operations on loss of  
power. End of program or erase is detected by the  
Ready/Busy status pin, Data Polling of DQ7, or by the  
Toggle Bit I feature on DQ6. Once the program or erase  
cycle has been successfully completed, the device  
internally resets to the Read mode.  
The F49L004UA/ F49L004BA is entirely pin and  
command set compatible with the JEDEC standard for 4  
Megabit Flash memory devices. Commands are written to  
the command register using standard microprocessor  
write timings.  
Elite Flash Storage Technology Inc.  
Publication Date : Sep. 2003  
Revision: 1.0  
1/46  
1234567...46

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F49L004UA-70NP ESMT

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