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F25L08PA_1 PDF预览

F25L08PA_1

更新时间: 2024-02-17 03:57:50
品牌 Logo 应用领域
晶豪 - ESMT 闪存
页数 文件大小 规格书
32页 490K
描述
3V Only 8 Mbit Serial Flash Memory with Dual

F25L08PA_1 数据手册

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ESMT  
Flash  
F25L08PA  
Operation Temperature Condition -40°C~85°C  
3V Only 8 Mbit Serial Flash Memory with Dual  
„ FEATURES  
y
y
Single supply voltage 2.7~3.6V  
Standard, Dual SPI  
y
y
Page Programming  
- 256 byte per programmable page  
y
Speed  
Auto Address Increment (AAI) WORD Programming  
- Decrease total chip programming time over  
Byte Program operations  
- Read max frequency: 33MHz  
- Fast Read max frequency: 50MHz; 100MHz  
- Fast Read Dual max frequency: 50MHz / 100MHz  
(100MHz / 200MHz equivalent Dual SPI)  
y
y
Lockable 4K bytes OTP security sector  
y
Low power consumption  
- Active current: 35 mA  
- Standby current: 30μ A  
SPI Serial Interface  
- SPI Compatible: Mode 0 and Mode 3  
y
y
End of program or erase detection  
Write Protect ( WP )  
y
y
Reliability  
- 100,000 typical program/erase cycles  
- 20 years Data Retention  
y
y
Hold Pin (HOLD )  
Program  
All Pb-free products are RoHS-Compliant  
- Byte programming time: 7μ s (typical)  
- Page programming time: 1.5 ms (typical)  
y
Erase  
- Chip erase time 10 sec (typical)  
- Block erase time 1 sec (typical)  
- Sector erase time 90 ms (typical)  
„ ORDERING INFORMATION  
Product ID  
Speed  
Package  
COMMENTS  
Pb-free  
F25L08PA –50PIG  
F25L08PA –100PIG  
F25L08PA –50PAIG  
50MHz 8 lead SOIC  
100MHz 8 lead SOIC  
50MHz 8 lead SOIC  
150mil  
150mil  
200mil  
200mil  
300mil  
300mil  
Pb-free  
Pb-free  
F25L08PA –100PAIG 100MHz 8 lead SOIC  
Pb-free  
F25L08PA –50DIG  
F25L08PA –100DIG  
50MHz 8 lead PDIP  
100MHz 8 lead PDIP  
Pb-free  
Pb-free  
„ GENERAL DESCRIPTION  
The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash  
memory device. The device supports the standard Serial  
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory  
devices reliably store memory data even after 100,000  
programming and erase cycles.  
The device features sector erase architecture. The memory array  
is divided into 256 uniform sectors with 4K byte each; 16 uniform  
blocks with 64K byte each. Sectors can be erased individually  
without affecting the data in other sectors. Blocks can be erased  
individually without affecting the data in other blocks. Whole chip  
erase capabilities provide the flexibility to revise the data in the  
device. The device has Sector, Block or Chip Erase but no page  
erase.  
The memory array can be organized into 4,096 programmable  
pages of 256 byte each. 1 to 256 byte can be programmed at a  
time with the Page Program instruction. The device also can be  
programmed to decrease total chip programming time with Auto  
Address Increment (AAI) programming.  
The sector protect/unprotect feature disables both program and  
erase operations in any combination of the sectors of the  
memory.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jul. 2009  
Revision: 1.3  
1/32  

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