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F25L04PA-86PAG2D PDF预览

F25L04PA-86PAG2D

更新时间: 2023-01-15 00:00:00
品牌 Logo 应用领域
晶豪 - ESMT 光电二极管
页数 文件大小 规格书
33页 328K
描述
Flash, 4MX1, PDSO8, 0.208 INCH, 1.27 MM PITCH, ROHS COMPLIANT, SOIC-8

F25L04PA-86PAG2D 数据手册

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ESMT  
F25L04PA (2D)  
Flash  
3V Only 4 Mbit Serial Flash Memory  
with Dual Output  
FEATURES  
Single supply voltage 2.3~3.6V  
Standard, Dual SPI  
Erase  
- Chip erase time 1 sec (typical)  
- Block erase time 0.15 sec (typical)  
- Sector erase time 30 ms (typical)  
Speed  
- Read max frequency: 33MHz  
- Fast Read max frequency: 50MHz; 86MHz; 100MHz  
- Fast Read Dual max frequency: 50MHz / 86MHz  
(100MHz / 172MHz equivalent Dual SPI)  
Page Programming  
- 256 byte per programmable page  
SPI Serial Interface  
- SPI Compatible: Mode 0 and Mode 3  
Low power consumption  
- Active current: 20 mA  
- Standby current: 25μ A  
End of program or erase detection  
Write Protect ( WP )  
- Deep Power Down current: 10μ A  
Reliability  
Hold Pin (HOLD )  
- 100,000 typical program/erase cycles  
- 20 years Data Retention  
All Pb-free products are RoHS-Compliant  
Program  
- Page programming time: 0.7 ms (typical)  
ORDERING INFORMATION  
Product ID  
Speed  
Package  
Comments  
F25L04PA –50PG2D  
F25L04PA –86PG2D  
F25L04PA –100PG2D  
F25L04PA –50PAG2D  
F25L04PA –86PAG2D  
50MHz  
86MHz  
100MHz  
50MHz  
86MHz  
8-lead  
SOIC  
150 mil  
200 mil  
6x5 mm  
Pb-free  
8-lead  
SOIC  
Pb-free  
Pb-free  
F25L04PA –100PAG2D 100MHz  
F25L04PA –50HG2D  
F25L04PA –86HG2D  
F25L04PA –100HG2D  
50MHz  
86MHz  
100MHz  
8-contact  
WSON  
GENERAL DESCRIPTION  
The F25L04PA is a 4Megabit, 3V only CMOS Serial Flash  
memory device. The device supports the standard Serial  
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory  
devices reliably store memory data even after 100,000  
programming and erase cycles.  
is divided into 128 uniform sectors with 4K byte each; 8 uniform  
blocks with 64K byte each. Sectors can be erased individually  
without affecting the data in other sectors. Blocks can be erased  
individually without affecting the data in other blocks. Whole chip  
erase capabilities provide the flexibility to revise the data in the  
device. The device has Sector, Block or Chip Erase but no page  
erase.  
The memory array can be organized into 2,048 programmable  
pages of 256 byte each. 1 to 256 byte can be programmed at a  
time with the Page Program instruction.  
The sector protect/unprotect feature disables both program and  
erase operations in any combination of the sectors of the  
memory.  
The device features sector erase architecture. The memory array  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Aug. 2012  
Revision: 1.4  
1/33  

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