Sampling IF Receiver 600MHz to
1000MHz
F0502
Datasheet
FEATURES
DESCRIPTION
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Dual Channel for Diversity / MIMO Systems
This document describes the specifications for the F0502
600MHz to 1000MHz dual path Sampling IF (SIF)
Receiver used in Multi-mode, Multi-carrier BaseStation
Receivers. Refer to the Part Number# Matrix below
describing the frequency coverage of the complete series.
This series is offered with high side or low side LO
injection options for all UTRA bands and offers
significantly better Noise and Distortion performance than
currently available solutions. IF frequencies from 60MHz
to 275MHz are supported.
Combines FlatNoiseTM and Zero- DistortionTM
technology
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28.2dB Total Power Gain
47dB gain control range
1dB Gain Steps
Ultra linear +44dBm IP3O
Low NF: 9.6dB at GMAX
50Ω input impedance
Matched 100Ω differential output impedance
Ultra high +20.2dBm P1dBo
Independent path standby mode
Constant LO impedance in STBY mode
6 bit parallel control
60MHz to 275MHz IF frequency range
Excellent 2nd Harmonic Rejection
ICC = 480mA STD Mode, 390mA LC Mode
10 x 10 mm 68-pin VFQFPN package
The F0502 SIF provides 28.2dB gain and offers 47dB
gain adjustment in 1dB steps and is designed to operate
with a single 5V supply. Nominally, the device offers
+44dBm Output IP3 using 480mA of ICC. Alternately one
can configure the device in low current (LC) mode to
reduce power consumption to less than 1.95 watts.
This device is packaged in a 10x10 68-pin TQFN with
50Ω single-ended RF input and 200Ω differential IF
output impedances for ease of integration into the
receiver lineup. The 200Ω differential IF output can
easily be matched to 100Ω differential per the
application drawing.
DEVICE BLOCK DIAGRAM
RFIN_A
IFOUT_A+
IFOUT_A-
COMPETITIVE ADVANTAGE
Renesas’ Zero-DistortionTM mixer in combination with
interstage filtering and Renesas’ proprietary FlatNoiseTM
DVGA improves system SNR to the point where the
external SAW filter can be eliminated. Both IP3O and NF
are kept virtually flat while gain is backed off, enhancing
SNR significantly under high level interferer conditions,
and greatly benefiting 2G/3G/4G Multi-Carrier IF
6
2
6
G AIN _A[0:5]
TDD (STBY )
G AIN _B[0:5]
LC_Mode
Iset
LO VCO
Decode
Logic
Bias
Control
2
IFOUT_B+
RFIN_B
IFOUT_B-
sampling receivers. In addition, total power consumption
is reduced by 35% compared to conventional solutions.
No external SAW is needed
PART NUMBER# MATRIX
Reduced Power Consumption by 35%
Part#
RF Freq
Range
(MHz)
UTRA bands
IF Freq
Range
(MHz)
Typ.
Gain
(dB)
Injection
NF and OIP3 virtually flat for first 13dB gain
reduction
5,6,8,12,13,14,17
18,19,20
Low &
High Side
F0502
F0552
F0562
600 - 1000
1710 - 2050
2300 – 2700
60 - 275
60 – 450
60 – 450
28.2
29
The fast-settling, parallel mode gain step of 1.0 dB
coupled with the excellent differential non-linearity allow
for SNR to be maximized further by targeting the
minimum necessary gain in small, accurate increments.
The matched output does not require a terminating
resistor, thus the gain and distortion performance are
preserved when driving Bandpass Anti-Alias filters.
1,2,3,4,9,10,23,
25,33,34,35,36,
37,39
Low &
High Side
Low &
High Side
7,38,40,41
29
FlatNoiseTM, Zero-DistortionTM, SIF Rx
1
February 8,2022
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