Dual, 16-/12-Bit nanoDAC+
with 2 ppm/°C Reference, SPI Interface
Data Sheet
AD5689R/AD5687R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
GND
High relative accuracy (INL): 2 LSB maximum at 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
AD5689R/AD5687R
VLOGIC
SCLK
2.5V
REFERENCE
INPUT
DAC
STRING
DAC A
VOUT
A
B
TUE: 0.1% of FSR maximum
Offset error: 1.5 mV maximum
REGISTER
REGISTER
SYNC
SDIN
BUFFER
BUFFER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
VOUT
Gain error: 0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
SDO
POWER-ON
RESET
GAIN =
×1/×2
POWER-
DOWN
LOGIC
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD ratings
Low power: 3.3 mW at 3 V
RSTSEL
GAIN
LDAC RESET
Figure 1.
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5689R/AD5687R members of the nanoDAC+™
family are low power, dual, 16-/12-bit buffered voltage output
digital-to-analog converters (DACs). The devices include
a 2.5 V, 2 ppm/°C internal reference (enabled by default)
and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic
by design, and exhibit less than 0.1% FSR gain error and
1.5 mV offset error performance. Both devices are available
in a 3 mm × 3 mm LFCSP and a TSSOP package.
Table 1. Dual nanoDAC+ Devices
Interface
Reference
Internal
External
Internal
External
16-Bit
AD5689R
AD5689
N/A
12-Bit
SPI
AD5687R
AD5687
AD5697R
N/A
I2C
N/A
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5689R (16-bit): 2 LSB maximum
AD5687R (12-bit): 1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
The AD5689R/AD5687R also incorporate a power-on reset
circuit and a RSTSEL pin that ensure that the DAC outputs
power up to zero scale or midscale and remain there until
a valid write takes place. Each part contains a per channel
power-down feature that reduces the current consumption
of the device to 4 µA at 3 V while in power-down mode.
The AD5689R/AD5687R use a versatile serial peripheral
interface (SPI) that operates at clock rates up to 50 MHz.
and both devices contain a VLOGIC pin that is intended for
1.8 V/3 V/5 V logic.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com