FHX04X, FHX05X, FHX06X
GaAs FET & HEMT Chips
FEATURES
• Low Noise Figure: 0.75dB (Typ.)@f=12GHz (FHX04)
• High Associated Gain: 10.5dB (Typ.)@f=12GHz
• Lg ≤ 0.25µm, Wg = 200µm
• Gold Gate Metallization for High Reliability
DESCRIPTION
The FHX04X, FHX05X, FHX06X are High Electron Mobility
Transistors (HEMT) intended for general purpose, low noise and high
gain amplifiers in the 2-18GHz frequency range. The devices are well
suited for telecommunication, DBS, TVRO, VSAT or other low noise
applications.
Eudyna’s stringent Quality Assurance Program assures the highest
reliability and consistent performance.
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Item
Symbol
Unit
Rating
V
Drain-Source Voltage
3.5
-3.0
V
V
DS
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
V
GS
P
180
mW
°C
°C
t*
T
-65 to +175
175
stg
T
ch
*Note: Mounted on Al O board (30 x 30 x 0.65mm)
2
3
Eudyna recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (V ) should not exceed 2 volts.
DS
2. The forward and reverse gate currents should not exceed 0.2 and -0.05 mA respectively with
gate resistance of 4000Ω.
3. The operating channel temperature (T ) should not exceed 80°C.
ch
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Limit
Typ.
30
45
Item
Symbol
Test Conditions
= 2V, V = 0V
Unit
Min.
15
35
Max.
60
-
-1.5
-
I
V
V
V
Saturated Drain Current
Transconductance
mA
mS
V
DSS
DS
DS
DS
GS
GS
g
= 2V, I
= 2V, I
= 10mA
m
DS
Pinch-off Voltage
Gate Source Breakdown Voltage
Noise Figure
V
= 1mA
-0.2 -0.7
p
DS
V
I
= -10µA
-3.0
-
9.5
-
9.5
-
-
V
GSO
NF
0.75 0.85
10.5
0.9
10.5
1.1
dB
dB
dB
dB
dB
dB
FHX04X
Associated Gain
G
as
NF
-
1.1
-
V
= 2V
= 10mA
DS
Noise Figure
FHX05X
I
DS
Associated Gain
G
as
f = 12GHz
Noise Figure
FHX06X
NF
1.35
-
Associated Gain
G
9.5
10.5
as
Same as above,
Gain matched
G (max)
a
Maximum Available Gain
Thermal Resistance
11.0 12.0
220
-
dB
R
Channel to Case
-
300
°C/W
th
Note: RF parameter sample size 10pcs. criteria (accept/reject)=(2/3)
The chip must be enclosed in a hermetically sealed environment for optimum performance and reliability.
Edition 1.3
October 2004
1