5秒后页面跳转
EPM7256AEFC100-10N PDF预览

EPM7256AEFC100-10N

更新时间: 2024-01-22 07:54:42
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
64页 1018K
描述
Programmable Logic Device

EPM7256AEFC100-10N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:FINE LINE, BGA-100针数:100
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.39.00.01风险等级:5.1
其他特性:YES最大时钟频率:95.2 MHz
系统内可编程:YESJESD-30 代码:S-PBGA-B100
JESD-609代码:e1JTAG BST:YES
长度:11 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:84
宏单元数:256端子数量:100
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 84 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA100,10X10,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:1.7 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:11 mm
Base Number Matches:1

EPM7256AEFC100-10N 数据手册

 浏览型号EPM7256AEFC100-10N的Datasheet PDF文件第2页浏览型号EPM7256AEFC100-10N的Datasheet PDF文件第3页浏览型号EPM7256AEFC100-10N的Datasheet PDF文件第4页浏览型号EPM7256AEFC100-10N的Datasheet PDF文件第5页浏览型号EPM7256AEFC100-10N的Datasheet PDF文件第6页浏览型号EPM7256AEFC100-10N的Datasheet PDF文件第7页 
MAX 7000A  
Programmable Logic  
Device  
Includes  
MAX 7000AE  
®
September 2003, ver. 4.5  
Data Sheet  
High-performance 3.3-V EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
MAX 7000AE device in-system programmability (ISP) circuitry  
compliant with IEEE Std. 1532  
EPM7128A and EPM7256A device ISP circuitry compatible with  
IEEE Std. 1532  
Built-in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
Supports JEDEC Jam Standard Test and Programming Language  
(STAPL) JESD-71  
Enhanced ISP features  
Enhanced ISP algorithm for faster programming (excluding  
EPM7128A and EPM7256A devices)  
ISP_Done bit to ensure complete programming (excluding  
EPM7128A and EPM7256A devices)  
Pull-up resistor on I/O pins during in-system programming  
Pin-compatible with the popular 5.0-V MAX 7000S devices  
High-density PLDs ranging from 600 to 10,000 usable gates  
Extended temperature range  
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V  
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.  
f
Altera Corporation  
1
DS-M7000A-4.5  

与EPM7256AEFC100-10N相关器件

型号 品牌 描述 获取价格 数据表
EPM7256AEFC100-12 ALTERA EE PLD, 12ns, CMOS, PBGA100, FBGA-100

获取价格

EPM7256AEFC100-4 ALTERA EE PLD, 4.5ns, CMOS, PBGA100

获取价格

EPM7256AEFC100-5 INTEL EE PLD, 5.5ns, 256-Cell, CMOS, PBGA100, FINE LINE, BGA-100

获取价格

EPM7256AEFC100-5N INTEL EE PLD, 5.5ns, CMOS, PBGA100, FINE LINE, BGA-100

获取价格

EPM7256AEFC100-7 ALTERA EE PLD, 7.5ns, 256-Cell, CMOS, PBGA100, FINE LINE, BGA-100

获取价格

EPM7256AEFC100-7 INTEL EE PLD, 7.5ns, 256-Cell, CMOS, PBGA100, FINE LINE, BGA-100

获取价格