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EPM7128SQC100-15C PDF预览

EPM7128SQC100-15C

更新时间: 2024-11-21 13:07:39
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件输入元件LTE时钟
页数 文件大小 规格书
66页 1497K
描述
EE PLD, 15ns, CMOS, PQFP100, PLASTIC, QFP-100

EPM7128SQC100-15C 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56其他特性:CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
最大时钟频率:76.9 MHzJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
专用输入次数:I/O 线路数量:80
端子数量:100最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 80 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:RECTANGULAR
封装形式:FLATPACK可编程逻辑类型:EE PLD
传播延迟:15 ns认证状态:Not Qualified
座面最大高度:3.65 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

EPM7128SQC100-15C 数据手册

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MAX 7000  
Programmable Logic  
Device Family  
®
September 2005, ver. 6.7  
Data Sheet  
High-performance, EEPROM-based programmable logic devices  
(PLDs) based on second-generation MAX® architecture  
5.0-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in  
MAX 7000S devices  
Features...  
ISP circuitry compatible with IEEE Std. 1532  
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S  
devices  
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S  
devices with 128 or more macrocells  
Complete EPLD family with logic densities ranging from 600 to  
5,000 usable gates (see Tables 1 and 2)  
5-ns pin-to-pin logic delays with up to 175.4-MHz counter  
frequencies (including interconnect)  
PCI-compliant devices available  
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V  
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data  
Sheet.  
f
Table 1. MAX 7000 Device Features  
Feature  
EPM7032  
EPM7064  
EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E  
Usable  
600  
1,250  
1,800  
2,500  
3,200  
3,750  
5,000  
gates  
Macrocells  
32  
2
64  
4
96  
6
128  
8
160  
10  
192  
12  
256  
16  
Logic array  
blocks  
Maximum  
36  
68  
76  
100  
104  
124  
164  
user I/O pins  
t
PD (ns)  
tSU (ns)  
FSU (ns)  
tCO1 (ns)  
CNT (MHz)  
6
5
6
5
7.5  
6
7.5  
6
10  
12  
7
12  
7
7
3
t
2.5  
4
2.5  
4
3
3
3
3
4.5  
125.0  
4.5  
125.0  
5
6
6
f
151.5  
151.5  
100.0  
90.9  
90.9  
Altera Corporation  
1
DS-MAX7000-6.7  

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