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EPM570ZM144A6N PDF预览

EPM570ZM144A6N

更新时间: 2024-11-06 06:52:51
品牌 Logo 应用领域
英特尔 - INTEL LTE输入元件可编程逻辑
页数 文件大小 规格书
86页 1210K
描述
Flash PLD, 9.5ns, 440-Cell, CMOS, PBGA144, LEAD FREE, MICRO, FBGA-144

EPM570ZM144A6N 数据手册

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Section I. MAX II Device Family Data  
Sheet  
®
This section provides designers with the data sheet specifications for MAX II devices.  
The chapters contain feature definitions of the internal architecture, Joint Test Action  
Group (JTAG) and in-system programmability (ISP) information, DC operating  
conditions, AC timing parameters, and ordering information for MAX II devices.  
This section includes the following chapters:  
Chapter 1, Introduction  
Chapter 2, MAX II Architecture  
Chapter 3, JTAG and In-System Programmability  
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices  
Chapter 5, DC and Switching Characteristics  
Chapter 6, Reference and Ordering Information  
Revision History  
Refer to each chapter for its own specific revision history. For information about when  
each chapter was updated, refer to the Chapter Revision Dates section, which appears  
in the complete handbook.  
© October 2008 Altera Corporation  
MAX II Device Handbook  

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