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EPM570GF256C3N PDF预览

EPM570GF256C3N

更新时间: 2024-02-04 17:57:53
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
6页 86K
描述
Flash PLD, 5.4ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256

EPM570GF256C3N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256针数:256
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5
其他特性:IT CAN ALSO OPERATE AT 3.3V系统内可编程:YES
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
JTAG BST:YES长度:17 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:160宏单元数:440
端子数量:256最高工作温度:85 °C
最低工作温度:组织:0 DEDICATED INPUTS, 160 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260电源:1.5/3.3,1.8 V
可编程逻辑类型:FLASH PLD传播延迟:5.4 ns
认证状态:Not Qualified座面最大高度:2.2 mm
子类别:Programmable Logic Devices最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:17 mmBase Number Matches:1

EPM570GF256C3N 数据手册

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1. Introduction  
MII51001-1.9  
Introduction  
®
The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-µm,  
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128  
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices  
offer high I/O counts, fast performance, and reliable fitting versus other CPLD  
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and  
enhanced in-system programmability (ISP), MAX II devices are designed to reduce  
cost and power while providing programmable solutions for applications such as bus  
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device  
configuration control.  
Features  
The MAX II CPLD has the following features:  
Low-cost, low-power CPLD  
Instant-on, non-volatile architecture  
Standby current as low as 25 µA  
Provides fast propagation delay and clock-to-output times  
Provides four global clocks with two clocks available per logic array block (LAB)  
UFM block up to 8 Kbits for non-volatile storage  
MultiVolt core enabling external supply voltages to the device of either  
3.3 V/2.5 V or 1.8 V  
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels  
Bus-friendly architecture including programmable slew rate, drive strength,  
bus-hold, and programmable pull-up resistors  
Schmitt triggers enabling noise tolerant inputs (programmable per pin)  
I/Os are fully compliant with the Peripheral Component Interconnect Special  
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V  
operation at 66 MHz  
Supports hot-socketing  
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry  
compliant with IEEE Std. 1149.1-1990  
ISP circuitry compliant with IEEE Std. 1532  
© August 2009 Altera Corporation  
MAX II Device Handbook  

EPM570GF256C3N 替代型号

型号 品牌 替代类型 描述 数据表
EPM570GF256C5N ALTERA

完全替代

The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m,
EPM570GF256C3 ALTERA

完全替代

The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m,

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Flash PLD, 7ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
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Flash PLD, 7ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
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EPM570GM100A3N INTEL

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MAX II Device Family