Includes
FLEX 10KA
FLEX 10K
Embedded Programmable
Logic Device Family
®
March 2001, ver. 4.1
Data Sheet
ꢀ
The industry’s first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
integration
Features...
–
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
Logic array for general logic functions
–
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High density
–
–
10,000 to 250,000 typical gates (see Tables 1 and 2)
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
–
–
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MultiVoltTM I/ O interface support
5.0-V tolerant input pins in FLEX® 10KA devices
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
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FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG) PCI
Local Bus Specification, Revision 2.2
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–
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FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
EPF10K10
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K10A
EPF10K30A
EPF10K50V
Typical gates (logic and RAM) (1)
Maximum system gates
Logic elements (LEs)
10,000
31,000
576
20,000
63,000
1,152
144
30,000
69,000
1,728
216
40,000
93,000
2,304
288
50,000
116,000
2,880
360
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
72
3
6
6
8
10
6,144
150
12,288
189
12,288
246
16,384
189
20,480
310
Maximum user I/O pins
Altera Corporation
1
A-DS-F10K-04.1