SLVU2.8-8
EPD TVS™ Diode Array
For ESD and Latch-Up Protection
PRELIMINARY
PROTECTION PRODUCTS
Features
Description
The SLV series of transient voltage suppressors are
designed to protect low voltage, state-of-the-art CMOS
semiconductors from transients caused by electro-
static discharge (ESD), cable discharge events (CDE),
lightning and other induced voltage surges.
600 Watts peak pulse power (tp = 8/20µs)
Transient protection for high speed data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)
IEC 61000-4-5 (Lightning) 24A (tp = 8/20µs)
Protects four line pairs (eight lines)
Comprehensive pin out for easy board layout
Low capacitance
High peak pulse current (30A, 8/20µs)
Low leakage current
Low operating and clamping voltages
Solid-state EPD TVS process technology
The devices are constructed using Semtech’s propri-
etary EPD process technology. The EPD process pro-
vides low standoff voltages with significant reductions
in leakage currents and capacitance over silicon-
avalanche diode processes. The SLVU2.8-8 features
integrated low capacitance compensation diodes that
reduce the maximum capacitance to 8pF per line.
This, combined with low leakage current, means signal
integrity is preserved in high-speed applications such
as 10/100/1000 Ethernet.
Mechanical Characteristics
JEDEC SO-8 package
The SLVU2.8-8 is in an SO-8 package and may be used
to protect four high-speed line pairs. The layout of the
device minimizes trace inductance and reduces voltage
overshoot associated with ESD events. The low
clamping voltage of the SLVU2.8-8 minimizes the
stress on the protected IC.
The SLV series TVS diodes will meet the surge require-
ments of IEC 61000-4-2 (ESD), IEC61000-4-5 (Light-
ning), and ETSI ETS 300 386.
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tape and Reel per EIA 481
Applications
10/100/1000 Ethernet
WAN/LAN Equipment
Switching Systems
DSLAMs
Desktops, Servers, & Notebooks
Instrumentation
Base Stations
Analog Inputs
Circuit Diagram (Each Line)
Schematic & PIN Configuration
SO-8 (Top View)
www.semtech.com
Revision 08/21/2002
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