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EPC1064LC20 PDF预览

EPC1064LC20

更新时间: 2024-02-07 05:31:07
品牌 Logo 应用领域
英特尔 - INTEL OTP只读存储器时钟内存集成电路
页数 文件大小 规格书
34页 420K
描述
Configuration Memory, 64KX1, Serial, MOS, PQCC20, PLASTIC, LCC-20

EPC1064LC20 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.61风险等级:5.6
其他特性:4 WIRE INTERFACE TO FLEX 8000 DEVICES最大时钟频率 (fCLK):4 MHz
I/O 类型:COMMONJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.9662 mm
内存密度:65536 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:1
功能数量:1端子数量:20
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX1
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:SERIAL峰值回流温度(摄氏度):220
电源:5 V认证状态:Not Qualified
座面最大高度:4.572 mm子类别:OTP ROMs
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:MOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:8.9662 mm
Base Number Matches:1

EPC1064LC20 数据手册

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5. Configuration Devices for  
SRAM-Based LUT Devices  
Data Sheet  
CF52005-2.1  
®
Configuration device family for configuring Stratix series,  
Features  
TM  
TM  
Cyclone series, APEX II, APEX 20K (including APEX 20K, APEX  
20KC, and APEX 20KE), Mercury , ACEX 1K, and FLEX (FLEX  
10KE, and FLEX 10KA) devices  
TM  
®
®
®
Easy-to-use 4-pin interface to Altera FPGAs  
Low current during configuration and near-zero standby current  
5.0-V and 3.3-V operation  
Software design support with the Altera Quartus II and  
®
®
MAX+PLUS II development systems for Windows-based PCs as  
well as Sun SPARCstation, and HP 9000 Series 700/800  
Programming support with the Altera Programming Unit (APU) and  
programming hardware from Data I/O, BP Microsystems, and other  
third-party programmers  
Available in compact plastic packages  
8-pin plastic dual in-line package (PDIP)  
20-pin plastic J-lead chip carrier (PLCC) package  
32-pin plastic thin quad flat pack (TQFP) package  
EPC2 device has reprogrammable Flash configuration memory  
5.0-V and 3.3-V in-system programmability (ISP) through the  
built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)  
interface  
Built-in JTAG boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
ISP circuitry is compatible with IEEE Std. 1532  
Supports programming through Serial Vector Format Files  
(.svf), Jam Standard Test and Programming Language (STAPL)  
Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the  
Quartus II and MAX+PLUS II software via the USB Blaster,  
TM  
TM  
MasterBlaster , ByteBlaster II, EthernetBlaster, or  
TM  
ByteBlasterMV download cable  
nINIT_CONFpin allows INIT_CONF JTAG instruction to  
initiate FPGA configuration  
Can be programmed with Programmer Object Files (.pof) for  
EPC1 and EPC1441 devices  
Available in 20-pin PLCC and 32-pin TQFP packages  
f
For detailed information on enhanced configuration devices, refer to  
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet. For  
detailed information on serial configuration devices, refer to Serial  
Configuration Devices (EPCS1, EPCS4, EPCS16, & EPCS64) Data Sheet.  
Altera Corporation  
August 2005  
5–1  

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