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EPC1064 PDF预览

EPC1064

更新时间: 2024-02-22 14:23:25
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
28页 358K
描述
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices

EPC1064 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:LQFP, QFP32,.35SQ,32Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.79最长访问时间:100 ns
最大时钟频率 (fCLK):4 MHzJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
内存密度:65536 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1功能数量:1
端子数量:32字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX1输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:SERIAL
峰值回流温度(摄氏度):235认证状态:Not Qualified
座面最大高度:1.27 mm串行总线类型:4-WIRE
最大待机电流:0.0001 A最大压摆率:0.01 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
Base Number Matches:1

EPC1064 数据手册

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Configuration Devices for  
ACEX, APEX, FLEX & Mercury Devices  
®
March 2001, ver. 11  
DataSheet  
Serial device family for configuring ACEXTM, APEXTM (including  
APEX 20K, APEX 20KC, and APEX 20KE), FLEX® (FLEX 10KE and  
FLEX 10KA), and MercuryTM devices  
Easy-to-use 4-pin interface to ACEX, APEX, FLEX, and Mercury  
devices  
Features  
Low current during configuration and near-zero standby current  
5.0-V and 3.3-V operation  
Software design support with the Altera® QuartusTM and  
MAX+PLUS® II development systems for Windows-based PCs as  
well as Sun SPARCstation, and HP 9000 Series 700/ 800  
Programming support with Alteras Master Programming Unit  
(MPU) and programming hardware from Data I/ O,  
BP Microsystems, and other manufacturers  
Available in compact plastic packages (see Figures 1 and 2)  
8-pin plastic dual in-line package (PDIP)  
20-pin plastic J-lead chip carrier (PLCC) package  
32-pin plastic thin quad flat pack (TQFP) package  
EPC2 device has reprogrammable Flash configuration memory  
5.0-V and 3.3-V in-system programmability (ISP) through the  
built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)  
interface  
Built-in JTAG boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
ISP circuitry is compatible with IEEE Std. 1532 for EPC2  
configuration device  
Supports programming through Serial Vector Format Files  
(.svf), JamTM Standard Test and Programming Language  
(STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the  
MAX+PLUS II software via the MasterBlasterTM  
,
ByteBlasterMVTM, or BitBlasterTM download cable  
nINIT_CONFpin allows a JTAG instruction to initiate APEX,  
FLEX, or Mercury device configuration  
Can be programmed with Programmer Object Files (.pof) for  
EPC1 and EPC1441 devices  
Available in 20-pin PLCC and 32-pin TQFP packages  
Altera Corporation  
1
A-DS-EPROM-11  

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