SO SMD 14 Pin 5 Tap TTL Compatible Active Delay Lines
TAP DELAYS
±5% or ±2 nS†
TOTAL DELAYS
±5% or ±2 nS†
PART
NUMBER
TAP DELAYS
±5% or ±2 nS†
TOTAL DELAYS
±5% or ±2 nS†
PART
NUMBER
5, 10, 15, 20
6, 12, 18, 24
7, 14, 21, 28
8, 16, 24, 32
9, 18, 27, 36
10, 20, 30, 40
12, 24, 36, 48
15, 30, 45, 60
25
30
35
40
45
50
60
75
EPA424-25
EPA424-30
EPA424-35
EPA424-40
EPA424-45
EPA424-50
EPA424-60
EPA424-75
20, 40, 60, 80
100
125
150
175
200
225
250
EPA424-100
EPA424-125
EPA424-150
EPA424-175
EPA424-200
EPA424-225
EPA424-250
25, 50, 75, 100
30, 60, 90, 120
35, 70, 105, 140
40, 80, 120, 160
45, 90, 135, 180
50, 100, 150, 200
†Whichever is greater.
Delay times referenced from input to leading edges at 25°C, 5.0V, with no load.
DC Electrical Characteristics
Parameter
Schematic
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
OH
V
V
V
µA
mA
mA
mA
OH
CC
IL
V
V
= min. V = min. I = max
0.5
-1.2
50
1.0
-2
OL
CC IH OL
14
12
10
6
8
VCC
4
OUTPUT
V
I
V
= min. I = II
K
IK
CC
I
High-Level Input Current
V
= max. V = 2.7V
IH
CC IN
V
= max. V = 5.25V
INPUT 1
CC
IN
= max. V = 0.5V
I
Low-Level Input Current
Short Circuit Output Current
V
IL
CC
IN
= max. V
I
V
= 0.
-40
-100
OS
CC OUT
GROUND
7
(One output at a time)
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
Fanout High-Level Output
Fanout Low-Level Output
V
= max. V = OPEN
75
75
4
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
T
V
CCL
CC
IN
Td £ 500 nS (0.75 to 2.4 Volts)
= max. V = 2.7V
RO
H
L
N
N
V
20 TTL LOAD
10 TTL LOAD
CC
OH
= max. V = 0.5V
V
CC
OL
Package Dimensions
Recommended
Operating Conditions
Min Max Unit
V
Supply Voltage
4.75
2.0
5.25
V
V
V
mA
mA
mA
%
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
.100
.24
I
I
I
.200
OL
Max.
PCA
EPA424-25
.155
P
*
40
.060
.275
W
d*
40
%
D.C.
.150
T
Operating Free-Air Temperature
-55
+125
°C
A
Suggested Solder
Pad Layout
.50
*These two values are inter-dependent.
.500 Max.
.004
Typ.
.235
Max.
Input Pulse Test Conditions @ 25° C
Unit
.228
.244
.02
.050
E
Pulse Input Voltage
3.2
110
2.0
1.0
100
5.0
Volts
%
nS
MHz
KHz
Volts
IN
P
W
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 200 nS
Pulse Repetition Rate @ Td > 200 nS
Supply Voltage
T
RI
P
RR
V
CC
DSA424 Rev. A 2/5/96
QAF-CSO1 Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
Fractional = ± 1/32
E L E C T R O N I C S I N C .
.XX = ± .030
.XXX = ± .010
FAX: (818) 894-5791
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