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EPA3507-500

更新时间： 2024-11-23 06:57:35
品牌 Logo 应用领域
PCA 延迟线逻辑集成电路PC
页数 文件大小 规格书
1页 44K
描述
14 Pin DIP and SMD 5 Tap Both Edges Controlled Fast Logic TTL Compatible Active Delay Lines

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中文翻译

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EPA3507-500 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.72Is Samacsys：N
JESD-30 代码：R-XDIP-T8JESD-609代码：e0
逻辑集成电路类型：ACTIVE DELAY LINE功能数量：1
抽头/阶步数：5端子数量：8
最高工作温度：70 °C最低工作温度：
输出极性：INVERTED封装主体材料：UNSPECIFIED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
可编程延迟线：NO认证状态：Not Qualified
座面最大高度：6.35 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总延迟标称（td）：500 ns
宽度：7.62 mmBase Number Matches：1

EPA3507-500 数据手册

  
14 Pin DIP and SMD 5 Tap Both Edges Controlled  
Fast Logic TTL Compatible Active Delay Lines  
Compatible with standard auto-insertable equipment and can be used in either infrared or vapor phase process.  
Input to Tap ± 5ꢀ or ± ±nS†  
Input to Tap ± 5ꢀ or ± ±nS†  
DIP Part  
Number  
DIP Part  
Number  
SMD Part  
Number  
SMD Part  
Number  
Tap to Tap ± ꢁꢀ or ± ±nS†  
Tap to Tap ± ꢁꢀ or ± ±nS†  
Tap  
Total  
Tap  
Total  
5, 10, 15, 20  
6, 12, 18, 24  
25  
30  
EPA3507-25  
EPA3507-30  
EPA3507-35  
EPA3507-40  
EPA3507-45  
EPA3507-50  
EPA3507-60  
EPA3507-75  
EPA3507-100  
EPA3507-125  
EPA3507-150  
EPA3507-175  
EPA3507G-25  
EPA3507G-30  
EPA3507G-35  
EPA3507G-40  
EPA3507G-45  
EPA3507G-50  
EPA3507G-60  
EPA3507G-75  
EPA3507G-100  
EPA3507G-125  
EPA3507G-150  
EPA3507G-175  
EPA3507-200  
EPA3507-225  
EPA3507G-200  
EPA3507G-225  
40, 80, 120, 160  
45, 90, 135, 180  
50, 100, 150, 200  
60, 120, 180, 240  
70, 140, 210, 280  
80, 160, 240, 320  
84, 168, 252, 336  
88, 176, 264, 352  
90, 180, 270, 360  
84, 188, 282, 376  
100, 200, 300, 400  
200  
225  
250  
300  
350  
400  
420  
440  
450  
470  
500  
7, 14, 21, 28  
8, 16, 24, 32  
35  
40  
EPA3507-250  
EPA3507-300  
EPA3507G-250  
EPA3507G-300  
9, 18, 27, 36  
45  
EPA3507-350  
EPA3507-400  
EPA3507-420  
EPA3507-440  
EPA3507-450  
EPA3507-470  
EPA3507-500  
EPA3507G-350  
EPA3507G-400  
EPA3507G-420  
EPA3507G-440  
EPA3507G-450  
EPA3507G-470  
EPA3507G-500  
10, 20, 30, 40  
12, 24, 36, 48  
50  
60  
15, 30, 45, 60  
75  
20, 40, 60, 80  
25, 50, 75, 100  
100  
125  
30, 60, 90, 120  
35, 70, 105, 140  
150  
175  
†Whichever is greater.  
Delay measured @ 1.5V levels on leading and trailing edge w/ 15pF load on taps.  
Rise and Fall Time measured from 0.75 to 2.4V level.  
Electrical Characteristics  
Parameter  
Schematic  
Test Conditions  
Min. Max. Unit  
V
V
V
High-Level Output Voltage  
Low-Level Output Voltage  
Input Clamp Voltage  
V
V
V
V
V
= Min. V = Max. I  
= Max. 2.7  
V
OH  
OL  
IK  
CC  
CC  
CC  
CC  
CC  
CC  
IL  
OH  
= Min. V = Min. I = Max.  
0.5  
-1.2  
20  
V
14  
12  
10  
6
8
VCC  
4
OUTPUT  
IH  
OL  
= Min. I  
= II  
V
I
K
I
High-Level Input Current  
Low-Level Input Current  
= Max. V = 2.7V  
µA  
mA  
mA  
IH  
IN  
INPUT 1  
I
= Max. V = 0.5V  
-0.6  
-150  
IL  
IN  
= Max. V  
I
Short Circuit Output Current V  
= 0.  
-60  
OS  
OUT  
(One output at a time)  
= Max. V = OPEN  
7
GROUND  
I
High-Level Supply Current  
Low-Level Supply Current  
Output Rise Time  
V
V
25  
40  
4
5
mA  
mA  
nS  
nS  
CCH  
CC  
CC  
IN  
I
= Max. V = 0  
IN  
CCL  
T
Td ≤ 500 nS (0.75 to 2.4 Volts)  
RO  
Td > 500 nS  
N
Fanout High-Level Output  
Fanout Low-Level Output  
Temp. Coeff. of Total Delay  
Storage Temp. Range  
V
V
= Max. V  
= Max. V  
= 2.7V  
= 0.5V  
20 TTL LOAD  
10 TTL LOAD  
H
CC  
CC  
OH  
OL  
Recommended  
Operating Conditions  
N
L
Min. Max.  
Unit  
T
T
100 + (25000ꢀTD) PPMꢀ°C  
C
-20 °C to +100 °C  
STG  
V
V
Supply Voltage  
4.75  
2.0  
V
V
5.25  
CC  
High-Level Input Voltage  
IH  
IL  
V
Low-Level Input Voltage  
Input Clamp Current  
0.8  
-18  
-1.0  
20  
V
Input Pulse Test Conditions @ ±5° C  
Unit  
I
I
mA  
IK  
High-Level Output Current  
Low-Level Output Current  
mA  
OH  
OL  
E
P
Pulse Input Voltage  
3.2  
---  
Volts  
nS  
IN  
W
I
mA  
%
Pulse Width 1.2X Total Delay  
Pulse Rise Time (10 - 90%)  
P
d*  
T
* Input Pulse Width of Total Delay  
Duty Cycle  
40  
0
W
T
3.0  
---  
nS  
RI  
%
50  
Pulse Repetition Rate 4X P  
W
P
RR  
CC  
MHz  
Volts  
Operating Free-Air Temperature  
°C  
+70  
A
V
Supply Voltage  
5.0  
*These two values are inter-dependent.  
SMD Package  
DIP Package  
.085  
Typ.  
.200  
.200  
PCA  
EPA3507-XX  
Date Code  
PCA  
EPA3507G-XX  
Date Code  
Pin 1  
I.D.  
Suggested Solder  
Pad Layout  
Pin 1  
I.D.  
.280  
Max.  
.055  
.420  
.270  
.300  
Typ.  
.200  
Typ.  
.300  
.780 Max.  
.100  
.300  
.030  
.770  
.020  
Min.  
.010  
.005  
.010  
Typ.  
.250  
Max.  
.215  
.019  
0°-8°  
.010  
Typ.  
.365  
Max.  
.035  
.380  
.020  
Typ.  
.100  
Typ.  
.125 .010  
.002  
DSA3507G-XX & DSA3507-XX Rev. - 7ꢀ22ꢀ98  
QAF-CSO1 Rev. B 8ꢀ25ꢀ94  
Unless Otherwise Noted Dimensions in Inches  
Tolerances:  
16799 SCHOENBORN ST.  
NORTH HILLS, CA 91343  
TEL: (818) 892-0761  
Fractional = 1ꢀ32  
E L E C T R O N I C S I N C .  
.XX = .030  
.XXX = .010  
FAX: (818) 894-5791  
1

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