1. Cyclone III Device Family Overview
CIII51001-1.1
The Cyclone® III FPGA family offered by Altera is a cost-optimized, memory-rich FPGA family.
Cyclone III FPGAs are built on TSMC's 65-nm low-power (LP) process technology with additional
silicon optimizations and software features to minimize power consumption. With this third
generation in the Cyclone series, Altera broadens the number of high volume, cost-sensitive
applications that can benefit from FPGAs.
Cyclone III:
Lowest
System-Cost
FPGAs
This chapter contains the following sections:
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“Cyclone III Device Features” on page 1–1
“Cyclone III Device Architecture” on page 1–4
“Reference and Ordering Information” on page 1–9
“Reference and Ordering Information” on page 1–9
Cyclone III devices are designed to offer low-power consumption and increased system integration
at reduced cost.
Cyclone III
Device Features
Reduced Cost
Cyclone III devices deliver the lowest device and system costs based on the following facts:
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Staggered I/O ring to lower die area
Wide range of low cost packages
Support for low-cost serial flash and commodity parallel flash devices for configuration
Lowest-Power 65-nm FPGA
Cyclone III devices are the lowest-power 65-nm FPGAs designed via TSMC’s 65-nm low power
process and Altera’s power aware design flow. Cyclone III devices support hot-socketing operation;
therefore, unused I/O banks can be powered down when the devices to which they are connected are
turned off. Benefits of the Cyclone III device's low-power operation include:
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Extended battery life for portable and handheld applications
Enabled operation in thermally challenged environments
Eliminated or reduced cooling system costs
Increased System Integration
Cyclone III devices provide increased system integration by offering the following features:
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Density is up to 119,088 logic elements (LEs) and memory is up to 3.8 Mbits. Refer to Table 1–1
on page 1–2.
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High memory to logic ratio for embedded DSP applications
Highest multiplier-to-logic ratio in the industry at every density; 260 MHz multiplier
performance
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High I/O count, low- and mid-range density devices for user I/O constrained applications
Up to four phase-locked loops (PLLs) provide robust clock management and synthesis for device
clocks, external system clocks, and I/O interfaces
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Up to five outputs per PLL
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Cascadable to save I/Os, ease PCB routing, and reduce the number of external reference
clocks needed
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Dynamically reconfigurable to change phase shift, frequency multiplication/division, and
input frequency in-system without reconfiguring the device
Altera Corporation
July 2007
1–1
Preliminary