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EP20K200CP240C7ES PDF预览

EP20K200CP240C7ES

更新时间: 2024-11-06 23:50:43
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ASIC

EP20K200CP240C7ES 数据手册

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APEX 20KC  
Programmable Logic  
Device  
®
February 2002 ver. 2.0  
Data Sheet  
Programmable logic device (PLD) manufactured using a 0.15-µm all-  
Features...  
layer copper-metal fabrication process  
25 to 35% faster design performance than APEXTM 20KE devices  
Pin-compatible with APEX 20KE devices  
High-performance, low-power copper interconnect  
MultiCoreTM architecture integrating look-up table (LUT) logic  
and embedded memory  
LUT logic used for register-intensive functions  
Embedded system blocks (ESBs) used to implement memory  
functions, including first-in first-out (FIFO) buffers, dual-port  
RAM, and content-addressable memory (CAM)  
High-density architecture  
200,000 to 1 million typical gates (see Table 1)  
Up to 38,400 logic elements (LEs)  
Up to 327,680 RAM bits that can be used without reducing  
available logic  
Table 1. APEX 20KC Device Features  
Note (1)  
Feature  
EP20K200C  
EP20K400C  
EP20K600C  
EP20K1000C  
Maximum system gates  
Typical gates  
526,000  
200,000  
8,320  
52  
1,052,000  
400,000  
16,640  
104  
1,537,000  
600,000  
24,320  
152  
1,772,000  
1,000,000  
38,400  
160  
LEs  
ESBs  
Maximum RAM bits  
PLLs (2)  
106,496  
2
212,992  
4
311,296  
4
327,680  
4
Speed grades (3)  
Maximum macrocells  
Maximum user I/O pins  
-7, -8, -9  
832  
-7, -8, -9  
1,664  
-7, -8, -9  
2,432  
-7, -8, -9  
2,560  
376  
488  
588  
708  
Notes:  
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to  
57,000 additional gates.  
(2) PLL: phase-locked loop.  
(3) The -7 speed grade provides the fastest performance.  
Altera Corporation  
1
DS-APEX20KC-2.0  

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