Datasheet > EP20K200CF672C9

EP20K200CF672C9

更新时间： 2024-09-17 23:50:43

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
88页	1103K
描述
ASIC

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EP20K200CF672C9 数据手册

APEX 20KC

Programmable Logic

Device

October 2001, ver. 1.2

Data Sheet

ꢀ

Programmable logic device (PLD) manufactured using a 0.15-µm all-

Features...

layer copper-metal fabrication process

–

25 to 35% faster design performance than APEX^TM20KE devices

Pin-compatible with APEX 20KE devices

High-performance, low-power copper interconnect

MultiCore^TMarchitecture integrating look-up table (LUT) logic

and embedded memory

–

LUT logic used for register-intensive functions

Embedded system blocks (ESBs) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port

RAM, and content-addressable memory (CAM)

ꢀ

High-density architecture

–

100,000 to 1.5 million typical gates (see Table 1)

Up to 51,840 logic elements (LEs)

Up to 442,368 RAM bits that can be used without reducing

available logic

Table 1. APEX 20KC Device Features

Note (1)

Feature

EP20K200C

EP20K400C

EP20K600C

EP20K1000C

EP20K1500C

Maximum system

gates

526,000

1,052,000

1,537,000

1,772,000

2,392,000

Typical gates

LEs

200,000

8,320

400,000

16,640

104

600,000

24,320

152

1,000,000

38,400

160

1,500,000

51,840

216

ESBs

Maximum RAM

bits

106,496

212,992

311,296

327,680

442,368

PLLs (2)

Speed grades (3)

-7, -8, -9

832

-7, -8, -9

1,664

-7, -8, -9

2,432

-7, -8, -9

2,560

-7, -8, -9

3,456

Maximum

macrocells

Maximum user I/O

pins

376

488

588

708

808

Notes:

(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to

57,000 additional gates.

(2) PLL: phase-locked loop.

(3) The -7 speed grade provides the fastest performance.

Altera Corporation

A-DS-APEX20KC-1.2

12 3 4 5 6 7...88

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EP20K200CF672C-9	INTEL	获取价格	Loadable PLD, PBGA672, 27 X 27 MM, 1 MM PITCH, FINE LINE, BGA-672
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