生命周期: | Active | 包装说明: | PGA, |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.77 | Is Samacsys: | N |
其他特性: | MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS | 最大时钟频率: | 28.6 MHz |
JESD-30 代码: | S-CPGA-P68 | JESD-609代码: | e0 |
专用输入次数: | 12 | I/O 线路数量: | 48 |
端子数量: | 68 | 最高工作温度: | 70 °C |
最低工作温度: | 组织: | 12 DEDICATED INPUTS, 48 I/O | |
输出函数: | MACROCELL | 封装主体材料: | CERAMIC, METAL-SEALED COFIRED |
封装代码: | PGA | 封装形状: | SQUARE |
封装形式: | GRID ARRAY | 可编程逻辑类型: | UV PLD |
传播延迟: | 40 ns | 最大供电电压: | 5.25 V |
最小供电电压: | 4.75 V | 标称供电电压: | 5 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | COMMERCIAL | 端子面层: | TIN LEAD |
端子形式: | PIN/PEG | 端子位置: | PERPENDICULAR |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
EP1810GC68-20 | ALTERA |
获取价格 |
UV PLD, 22ns, CMOS, CPGA68, CERAMIC, PGA-68 | |
EP1810GC68-35 | ALTERA |
获取价格 |
UV PLD, 40ns, 48-Cell, CMOS, CPGA68, CERAMIC, PGA-68 | |
EP1810GI-20 | ALTERA |
获取价格 |
UV PLD, 20ns, CPGA68, WINDOWED, CERAMIC, PGA-68 | |
EP1810GI-25 | ETC |
获取价格 |
UV-Erasable/OTP Complex PLD | |
EP1810GI-35 | ROCHESTER |
获取价格 |
HIGH PERFORMANCE COMPLEX EPLD featuring up to 64 inputs and 48 outputs | |
EP1810GI68-20 | ALTERA |
获取价格 |
UV PLD, 22ns, CMOS, CPGA68, CERAMIC, PGA-68 | |
EP1810GI68-25 | ALTERA |
获取价格 |
UV PLD, 28ns, CMOS, CPGA68, CERAMIC, PGA-68 | |
EP1810GM-45 | ALTERA |
获取价格 |
UV PLD, 50ns, 48-Cell, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68 | |
EP1810GM-45/883 | ALTERA |
获取价格 |
UV PLD, 55ns, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68 | |
EP1810GMB | ROCHESTER |
获取价格 |
HIGH PERFORMANCE COMPLEX EPLD featuring up to 64 inputs and 48 outputs |