Datasheet > EMF02P02H

EMF02P02H

更新时间： 2024-11-18 17:15:35

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
6页	206K
描述
EDFN5X6

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中文翻译

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数据手册

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EMF02P02H 数据手册

EMF02P02H

P‐Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BV^DSS

‐20V

3.2mΩ

‐100A

DSON (MAX.)

UIS, Rg 100% Tested

Pb‐Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±12

UNIT

Gate‐Source Voltage

V_GS

T_C= 25 °C

‐100

‐73

Continuous Drain Current¹

I_D

T_C= 100 °C

Pulsed Drain Current²

I_DM

I_AS

‐400

‐100

500

Avalanche Current

L = 0.1mH, ID=‐100A, RG=25Ω

L = 0.05mH

Avalanche Energy

E_AS

E_AR

Repetitive Avalanche Energy³

250

T_C= 25 °C

Power Dissipation

P_D

°C

T_C= 100 °C

Operating Junction & Storage Temperature Range

T_j, T_stg

‐55 to 150

100% UIS testing in condition of V_D=‐15V, L=0.1mH, V_G=‐5V, I_L=‐70A, Rated V_DS=‐20V P‐CH

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

Junction‐to‐Case

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

1.8

°C / W

Junction‐to‐Ambient⁴

R_JA

¹Package Limited.

²Pulse width limited by maximum junction temperature.

³Duty cycle  1％

⁴50°C / W when mounted on a 1 in²pad of 2 oz copper.

2016/3/15

p.1

12 3 4 5 6

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