Datasheet > EMDA0P10G

EMDA0P10G

更新时间： 2024-11-21 17:15:47

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
5页	177K
描述
SOP-8

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中文翻译

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数据手册

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EMDA0P10G 数据手册

EMDA0P10G

P‐Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BV^DSS

‐100V

120mΩ

‐3.4A

DSON (MAX.)

Pb‐Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±20

UNIT

Gate‐Source Voltage

V_GS

T_A= 25 °C

‐3.4

Continuous Drain Current

I_D

T_A= 70 °C

‐2.7

Pulsed Drain Current¹

I_DM

‐13.6

2.5

T_A= 25 °C

Power Dissipation

P_D

°C

T_A= 70 °C

1.6

Operating Junction & Storage Temperature Range

T_j, T_stg

‐55 to 150

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

Junction‐to‐Case

Junction‐to‐Ambient³

°C / W

R_JA

¹Pulse width limited by maximum junction temperature.

²Duty cycle  1％

³50°C / W when mounted on a 1 in²pad of 2 oz copper.

2016/9/1

p.1

12 3 4 5

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