Datasheet > EMD60N10A

EMD60N10A

更新时间： 2023-12-18 00:00:00

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
6页	231K
描述
NâChannel Logic Level Enhancement Mode Field Effect Transistor

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EMD60N10A 数据手册

EMD60N10A

N‐Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BV^DSS

RDSON (MAX.)

100V

60mΩ

20A

UIS, Rg 100% Tested

Pb‐Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_C= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±25

UNIT

Gate‐Source Voltage

V_GS

T_C= 25 °C

Continuous Drain Current

I_D

T_C= 100 °C

Pulsed Drain Current¹

I_DM

I_AS

Avalanche Current

L = 0.1mH, ID=20A, RG=25Ω

L = 0.05mH

Avalanche Energy

E_AS

E_AR

Repetitive Avalanche Energy²

T_C= 25 °C

Power Dissipation

P_D

°C

T_C= 100 °C

Operating Junction & Storage Temperature Range

T_j, T_stg

‐55 to 150

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

Junction‐to‐Case

4.0

°C / W

Junction‐to‐Ambient

R_JA

¹Pulse width limited by maximum junction temperature.

²Duty cycle  1％

2013/8/6

p.1

12 3 4 5 6

中文翻译

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