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EMB60C06V PDF预览

EMB60C06V

更新时间: 2024-05-23 22:23:34
品牌 Logo 应用领域
杰力科技 - EXCELLIANCE /
页数 文件大小 规格书
10页 640K
描述
EDFN3X3

EMB60C06V 数据手册

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EMB60C06V  
N-Channel + P-Channel Logic Level Enhancement Mode Field Effect Transistor  
▪Product Summary:  
▪ Pin Description:  
N-CH  
60V  
P-CH  
-60V  
BVDSS  
RDSON (MAX.)@VGS=10V  
RDSON (MAX.)@VGS=4.5V  
ID @TC=25  
60.0mΩ 90.0mΩ  
85.0mΩ 135.0mΩ  
13.0A  
4.0A  
-10.0A  
-4.0A  
ID @TA=25℃  
N + P Channel MOSFET  
UIS, Rg 100% Tested  
Pb-Free Lead Plating & Halogen Free  
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)  
PARAMETERS/TEST CONDITIONS SYMBOL  
Gate-Source Voltage  
LIMITS  
UNIT  
N-CH  
±20  
13  
P-CH  
±20  
-10  
-6  
VGS  
ID  
V
TC = 25 °C  
TC = 100 °C  
TA = 25 °C  
TA = 70 °C  
Continuous Drain Current  
8
4
3
52  
-4  
-3  
ID  
Continuous Drain Current  
A
Pulsed Drain Current1  
Avalanche Current  
IDM  
IAS  
-40  
-26  
33.8  
16.9  
16.7  
6.7  
2.3  
1.5  
25  
Avalanche Energy  
L = 0.1mH  
L = 0.05mH  
TC = 25 °C  
TC = 100 °C  
TA = 25 °C  
TA = 70 °C  
EAS  
EAR  
31.3  
15.6  
16.7  
6.7  
2.3  
1.5  
mJ  
W
Repetitive Avalanche Energy2  
PD  
Power Dissipation  
PD  
Power Dissipation  
W
°C  
Operating Junction & Storage Temperature Range  
Tj, Tstg  
-55 to 150  
100% UIS testing in condition of VD=30V, L=0.1mH, VG=10V, IL=15A, Rated VDS=60V N-CH  
100% UIS testing in condition of VD=30V, L=0.1mH, VG=10V, IL=16A, Rated VDS=-60V P-CH  
▪THERMAL RESISTANCE RATINGS  
MAXIMUM  
N-CH P-CH  
THERMAL RESISTANCE  
SYMBOL  
TYPICAL  
UNIT  
RθJC  
RθJA  
Junction-to-Case  
7.5  
55  
7.5  
55  
°C/W  
Junction-to-Ambient3  
1Pulse width limited by maximum junction temperature.  
2Duty cycle < 1%  
355°C / W when mounted on a 1 in2 pad of 2 oz copper.  
4Guarantee by Engineering test  
2020/9/8  
A.0  
P.1  

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