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EBE21UE8ACUA-8E-E PDF预览

EBE21UE8ACUA-8E-E

更新时间: 2024-01-21 14:03:48
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
27页 262K
描述
2GB DDR2 SDRAM SO-DIMM

EBE21UE8ACUA-8E-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SODIMM包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):400 MHz
I/O 类型:COMMONJESD-30 代码:R-XZMA-N200
内存密度:17179869184 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:200
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:256MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM200,24
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.16 A
子类别:DRAMs最大压摆率:3.04 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:0.6 mm
端子位置:ZIG-ZAG处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBE21UE8ACUA-8E-E 数据手册

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DATA SHEET  
2GB DDR2 SDRAM SO-DIMM  
EBE21UE8ACUA(256M words × 64 bits, 2 Ranks)  
Specifications  
Features  
Density: 2GB  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
256M words × 64 bits, 2 ranks  
Mounting 16 pieces of 1G bits DDR2 SDRAM sealed  
in FBGA  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
Package: 200-pin socket type small outline dual in  
line memory module (SO-DIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Differential clock inputs (CK and /CK)  
Lead-free (RoHS compliant)  
Power supply: VDD = 1.8V ± 0.1V  
Data rate: 800Mbps/667Mbps (max.)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Eight internal banks for concurrent operation  
(components)  
Data mask (DM) for write data  
Interface: SSTL_18  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Burst lengths (BL): 4, 8  
/CAS Latency (CL): 3, 4, 5, 6  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Precharge: auto precharge option for each burst  
/DQS can be disabled for single-ended Data Strobe  
access  
operation  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1217E10 (Ver. 1.0)  
Date Published November 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2007  

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