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EBE21UE8AADA-5C-E PDF预览

EBE21UE8AADA-5C-E

更新时间: 2024-02-19 02:34:07
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
21页 205K
描述
2GB DDR2 SDRAM SO-DIMM

EBE21UE8AADA-5C-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SODIMM包装说明:DIMM,
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.5 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-XZMA-N200内存密度:17179869184 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:200字数:268435456 words
字数代码:256000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:256MX64封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子位置:ZIG-ZAG
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

EBE21UE8AADA-5C-E 数据手册

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PRELIMINARY DATA SHEET  
2GB DDR2 SDRAM SO-DIMM  
EBE21UE8AADA (256M words × 64 bits, 2 Ranks)  
Description  
Features  
The EBE21UE8AADA is 256M words × 64 bits, 2 ranks  
200-pin socket type small outline dual in line memory  
module (SO-DIMM)  
DDR2 SDRAM Small Outline Dual In-line Memory  
Module, mounting 16 pieces of 1G bits DDR2 SDRAM  
with sFBGA stacking technology. Read and write  
operations are performed at the cross points of the CK  
and the /CK. This high-speed data transfer is realized  
by the 4 bits prefetch-pipelined architecture. Data  
strobe (DQS and /DQS) both for read and write are  
available for high speed and reliable data bus design.  
By setting extended mode register, the on-chip Delay  
Locked Loop (DLL) can be set enable or disable. This  
module provides high density mounting without utilizing  
surface mount technology. Decoupling capacitors are  
mounted beside each SDRAM on the module board.  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Lead-free (RoHS compliant)  
Power supply: VDD = 1.8V ± 0.1V  
Data rate: 533Mbps/400Mbps (max.)  
SSTL_18 compatible I/O  
Double-data-rate architecture: two data transfers per  
clock cycle  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
Note: Do not push the components or drop the  
modules in order to avoid mechanical defects,  
which may result in electrical defects.  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
Four internal banks for concurrent operation  
(Components)  
Data mask (DM) for write data  
Burst lengths: 4, 8  
/CAS Latency (CL): 3, 4, 5  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
/DQS can be disabled for single-ended Data Strobe  
operation.  
Document No. E0767E10 (Ver. 1.0)  
Date Published August 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2005  

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