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EBE21RD4ABHA-4A-E PDF预览

EBE21RD4ABHA-4A-E

更新时间: 2024-02-11 00:03:06
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
22页 173K
描述
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)

EBE21RD4ABHA-4A-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM240,40
针数:240Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N240内存密度:19327352832 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:240字数:268435456 words
字数代码:256000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:256MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM240,40封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.86 A子类别:DRAMs
最大压摆率:7.48 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:NO技术:CMOS
温度等级:OTHER端子形式:NO LEAD
端子节距:1 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED

EBE21RD4ABHA-4A-E 数据手册

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DATA SHEET  
2GB Registered DDR2 SDRAM DIMM  
EBE21RD4ABHA (256M words × 72 bits, 2 Ranks)  
Description  
Features  
The EBE21RD4ABHA is a 256M words × 72 bits, 2  
ranks DDR2 SDRAM Module, mounting 36 pieces of  
512M bits DDR2 SDRAM with sFBGA stacking  
technology. Read and write operations are performed  
at the cross points of the CK and the /CK. This high-  
speed data transfer is realized by the 4bits prefetch-  
pipelined architecture. Data strobe (DQS and /DQS)  
both for read and write are available for high speed and  
reliable data bus design. By setting extended mode  
register, the on-chip Delay Locked Loop (DLL) can be  
set enable or disable. This module provides high  
density mounting without utilizing surface mount  
240-pin socket type dual in line memory module  
(DIMM)  
PCB height: 30.0mm  
Lead pitch: 1.0mm  
Lead-free  
1.8V power supply  
Data rate: 533Mbps/400Mbps (max.)  
1.8 V (SSTL_18 compatible) I/O  
Double-data-rate architecture: two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS and /DQS) is  
transmitted /received with data, to be used in  
capturing data at the receiver  
technology.  
Decoupling capacitors are mounted  
beside each SDRAM on the module board.  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Note: Do not push the cover or drop the modules in  
order to avoid mechanical defects, which may  
result in electrical defects.  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Four internal banks for concurrent operation  
(Components)  
Burst length: 4, 8  
/CAS latency (CL): 3, 4, 5  
Auto precharge option for each burst access  
Auto refresh and self refresh modes  
7.8µs average periodic refresh interval  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
/DQS can be disabled for single-ended Data Strobe  
operation  
1 piece of PLL clock driver, 4 piece of register driver  
and 1 piece of serial EEPROM (2k bits EEPROM) for  
Presence Detect (PD)  
Document No. E0451E20 (Ver. 2.0)  
Date Published July 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2004  

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