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EBE11UD8AGSA-5C-E PDF预览

EBE11UD8AGSA-5C-E

更新时间: 2024-02-02 19:41:27
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
22页 207K
描述
1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)

EBE11UD8AGSA-5C-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SODIMM包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.5 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):267 MHzI/O 类型:COMMON
JESD-30 代码:R-XZMA-N200内存密度:8589934592 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:200字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:128MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM200,24封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.16 A子类别:DRAMs
最大压摆率:3.08 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:NO技术:CMOS
温度等级:OTHER端子形式:NO LEAD
端子节距:0.6 mm端子位置:ZIG-ZAG
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

EBE11UD8AGSA-5C-E 数据手册

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DATA SHEET  
1GB DDR2 SDRAM SO-DIMM  
EBE11UD8AGSA (128M words × 64 bits, 2 Ranks)  
Description  
Features  
The EBE11UD8AGSA is 128M words × 64 bits, 2 ranks  
DDR2 SDRAM Small Outline Dual In-line Memory  
Module, mounting 16 pieces of 512M bits DDR2  
SDRAM sealed in FBGA (µBGA) package. Read and  
write operations are performed at the cross points of  
the CK and the /CK. This high-speed data transfer is  
realized by the 4 bits prefetch-pipelined architecture.  
Data strobe (DQS and /DQS) both for read and write  
are available for high speed and reliable data bus  
design. By setting extended mode register, the on-chip  
Delay Locked Loop (DLL) can be set enable or disable.  
This module provides high density mounting without  
200-pin socket type small outline dual in line memory  
module (SO-DIMM)  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Lead-free (RoHS compliant)  
Power supply: VDD = 1.8V ± 0.1V  
Data rate: 667Mbps/533Mbps (max.)  
SSTL_18 compatible I/O  
Double-data-rate architecture: two data transfers per  
clock cycle  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
utilizing surface mount technology.  
Decoupling  
capacitors are mounted beside each FBGA (µBGA) on  
the module board.  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
Note: Do not push the components or drop the  
modules in order to avoid mechanical defects,  
which may result in electrical defects.  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
Four internal banks for concurrent operation  
(components)  
Data mask (DM) for write data  
Burst lengths: 4, 8  
/CAS Latency (CL): 3, 4, 5  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
/DQS can be disabled for single-ended Data Strobe  
operation  
Document No. E0827E10 (Ver. 1.0)  
Date Published October 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2005  

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