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EBD52UC8AKDA-7A PDF预览

EBD52UC8AKDA-7A

更新时间: 2024-01-09 11:12:27
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
19页 199K
描述
512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)

EBD52UC8AKDA-7A 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIMM,
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.75 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-XDMA-N200内存密度:4294967296 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:200字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64MX64封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

EBD52UC8AKDA-7A 数据手册

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PRELIMINARY DATA SHEET  
512MB DDR SDRAM SO DIMM  
EBD52UC8AKDA (64M words × 64 bits, 2 Ranks)  
Description  
Features  
The EBD52UC8AKDA is 64M words × 64 bits, 2 ranks  
Double Data Rate (DDR) SDRAM Small Outline Dual  
In-line Memory Module, mounting 16 pieces of 256M  
bits DDR SDRAM sealed in TCP package. Read and  
write operations are performed at the cross points of  
the CK and the /CK. This high-speed data transfer is  
realized by the 2 bits prefetch-pipelined architecture.  
Data strobe (DQS) both for read and write are available  
for high speed and reliable data bus design. By setting  
extended mode register, the on-chip Delay Locked  
Loop (DLL) can be set enable or disable. This module  
provides high density mounting without utilizing surface  
mount technology. Decoupling capacitors are mounted  
beside each TCP on the module board.  
200-pin socket type small outline dual in line memory  
module (SO DIMM)  
PCB height: 31.75mm  
Lead pitch: 0.6mm  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
Data inputs, outputs and DM are synchronized with  
DQS  
4 internal banks for concurrent operation  
Note: Do not push the cover or drop the modules in  
order to avoid mechanical defects, which may  
result in electrical defects.  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Data mask (DM) for write data  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0367E20 (Ver. 2.0)  
Date Published March 2003 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory , Inc. 2003  

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