Datasheet > 存储 > DRAM> EBD26UC6AKSA-6B

EBD26UC6AKSA-6B

更新时间： 2024-01-01 01:24:29

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	204K
描述
256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)

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EBD26UC6AKSA-6B 数据手册

PRELIMINARY DATA SHEET

256MB DDR SDRAM SO DIMM

EBD26UC6AKSA (32M words × 64 bits, 2 Banks)

Description

Features

The EBD26UC6AKSA is 32M words × 64 bits, 2 banks

Double Data Rate (DDR) SDRAM Small Outline Dual

In-line Memory Module, mounted 8 pieces of 256M bits

DDR SDRAM sealed in TSOP package. Read and

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. This module

provides high density mounting without utilizing surface

mount technology. Decoupling capacitors are mounted

beside each TSOP on the module board.

• 200-pin socket type small outline dual in line memory

module (SO DIMM)

PCB height: 31.75mm

Lead pitch: 0.6mm

• 2.5V power supply

• Data rate: 333Mbps/266Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs, outputs and DM are synchronized with

DQS

• 4 internal banks for concurrent operation

(Component)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)

7.8µs maximum average periodic refresh interval

• 2 variations of refresh

Auto refresh

Self refresh

Document No. E0307E20 (Ver. 2.0)

Date Published November 2002 (K) Japan

URL: http://www.elpida.com

Elpida Memory , Inc. 2002

12 3 4 5 6 7...19

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与EBD26UC6AKSA-6B相关器件

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EBD26UC6AKSA-6B-E	ELPIDA	256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)	获取价格
EBD26UC6AKSA-7A	ELPIDA	256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)	获取价格
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EBD26UC6AKSA-7B	ELPIDA	256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)	获取价格
EBD26UC6AKSA-7B-E	ELPIDA	256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)	获取价格
EBD26UC6AKSA-E	ELPIDA	256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)	获取价格