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EBD21RD4ADNA-7A-E PDF预览

EBD21RD4ADNA-7A-E

更新时间: 2024-02-27 12:28:35
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
19页 198K
描述
2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)

EBD21RD4ADNA-7A-E 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM,
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.92Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-XDMA-N184
JESD-609代码:e0内存密度:19327352832 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:184字数:268435456 words
字数代码:256000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256MX72封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):235
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBD21RD4ADNA-7A-E 数据手册

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DATA SHEET  
2GB Registered DDR SDRAM DIMM  
EBD21RD4ADNA-E (256M words × 72 bits, 2 Ranks)  
Description  
Features  
The EBD21RD4ADNA is a 256M words × 72 bits, 2  
184-pin socket type dual in line memory module  
(DIMM)  
ranks Double Data Rate (DDR) SDRAM Module,  
mounting 36 pieces of DDR SDRAM sealed in TCP  
package. Read and write operations are performed at  
the cross points of the CK and the /CK. This high-  
speed data transfer is realized by the 2-bit prefetch-  
pipelined architecture. Data strobe (DQS) both for  
read and write are available for high speed and reliable  
data bus design. By setting extended mode register,  
the on-chip Delay Locked Loop (DLL) can be set  
enable or disable. This module provides high density  
mounting without utilizing surface mount technology.  
Decoupling capacitors are mounted beside each TCP  
on the module board.  
PCB height: 30.48mm  
Lead pitch: 1.27mm  
Lead-free  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
Data inputs and outputs are synchronized with DQS  
Note: Do not push the cover or drop the modules in  
order to avoid mechanical defects, which may  
result in electrical defects.  
4 internal banks for concurrent operation  
(Components)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
1 piece of PLL clock driver, 1 piece of register driver  
and 1 piece of serial EEPROM (2k bits EEPROM) for  
Presence Detect (PD)  
Document No. E0606E10 (Ver. 1.0)  
Date Published October 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory,Inc. 2004  

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