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EBD11UD8ADDA-7A PDF预览

EBD11UD8ADDA-7A

更新时间: 2024-01-26 08:04:39
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
19页 205K
描述
1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

EBD11UD8ADDA-7A 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SODIMM包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.75 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-XZMA-N200内存密度:8589934592 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:200字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM200,24封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
电源:2.5 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.048 A子类别:DRAMs
最大压摆率:3.88 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.6 mm端子位置:ZIG-ZAG
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

EBD11UD8ADDA-7A 数据手册

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DATA SHEET  
1GB DDR SDRAM SO-DIMM  
EBD11UD8ADDA (128M words × 64 bits, 2 Ranks)  
Description  
Features  
The EBD11UD8ADDA is 128M words × 64 bits, 2  
ranks Double Data Rate (DDR) SDRAM Small Outline  
Dual In-line Memory Module, mounting 16 pieces of  
512M bits DDR SDRAM sealed in TCP package. Read  
and write operations are performed at the cross points  
of the CK and the /CK. This high-speed data transfer  
is realized by the 2 bits prefetch-pipelined architecture.  
Data strobe (DQS) both for read and write are available  
for high speed and reliable data bus design. By setting  
extended mode register, the on-chip Delay Locked  
Loop (DLL) can be set enable or disable. This module  
provides high density mounting without utilizing surface  
mount technology. Decoupling capacitors are mounted  
beside each TCP on the module board.  
200-pin socket type small outline dual in line memory  
module (SO-DIMM)  
PCB height: 31.75mm  
Lead pitch: 0.6mm  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
Data inputs, outputs and DM are synchronized with  
DQS  
4 internal banks for concurrent operation  
Note: Do not push the cover or drop the modules in  
order to avoid mechanical defects, which may  
result in electrical defects.  
(Components)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Data mask (DM) for write data  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0431E20 (Ver. 2.0)  
Date Published April 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2003-2004  

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