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ELANSC310-33KC PDF预览

ELANSC310-33KC

更新时间： 2024-11-19 03:34:07
品牌 Logo 应用领域
超微 - AMD 微控制器外围集成电路PC时钟
页数 文件大小 规格书
119页 1129K
描述
Single-Chip, 32-Bit, PC/AT Microcontroller

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中文翻译

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ELANSC310-33KC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：FQFP, QFP208,1.2SQ,20
针数：208Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.5
Is Samacsys：N具有ADC：NO
地址总线宽度：24位大小：32
最大时钟频率：25 MHzDAC 通道：NO
DMA 通道：YES外部数据总线宽度：16
JESD-30 代码：S-PQFP-G208JESD-609代码：e0
长度：28 mmI/O 线路数量：
端子数量：208最高工作温度：70 °C
最低工作温度：PWM 通道：NO
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP208,1.2SQ,20封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V认证状态：Not Qualified
ROM可编程性：FLASH座面最大高度：3.95 mm
速度：25 MHz子类别：Microprocessors
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

ELANSC310-33KC 数据手册

 浏览型号ELANSC310-33KC的Datasheet PDF文件第2页浏览型号ELANSC310-33KC的Datasheet PDF文件第3页浏览型号ELANSC310-33KC的Datasheet PDF文件第4页浏览型号ELANSC310-33KC的Datasheet PDF文件第5页浏览型号ELANSC310-33KC的Datasheet PDF文件第6页浏览型号ELANSC310-33KC的Datasheet PDF文件第7页 
PRELIMINARY  
Élan™SC310  
Single-Chip, 32-Bit, PC/AT Microcontroller  
n Integrated memory controller  
DISTINCTIVE CHARACTERISTICS  
– Controls symmetrically addressable DRAM or  
asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit  
DRAM or SRAM as main memory  
n Highly integrated, single-chip CPU and system  
logic  
– Optimized for embedded PC applications  
– Zero wait-state access with 70 ns, Page mode  
DRAMs  
– Combines 32 bit, x86 compatible, low-voltage  
CPU with memory controller, PC/AT peripheral  
controllers, real-time clock, and PLL clock  
generators  
– Supports up to 16 Mbyte system memory  
– Supports up to 16 Mbyte of application ROM/  
Flash, and 320 Kbyte direct ROM BIOS access.  
Also supports shadow RAM  
– 0.7 micron, low-voltage, CMOS process, fully  
static  
– Fully PC/AT compatible  
®
n Enhanced Am386 SXLV CPU core  
n Integrated PC/AT-lompatible leripheral logic  
– 25 MHz or 33 MHz operating frequencies  
– 3.3 V core, 3.3 V or 5 V memory and I/O  
– Low-power, fully static design for long battery life  
– One programmable interval timer (fully 8254  
compatible)  
– Two programmable interrupt controllers (8259A  
compatible)  
– System Management Mode (SMM) for power  
management control  
– Two DMA controllers (8237A compatible)  
n
Integrated power management functions  
– Built-in real-time clock (146818A compatible),  
with an additional 114 bytes of RAM  
– Internal clock generators (using multiple Phase-  
Locked Loops and one external 32-KHz crystal)  
– Internal Phase-Locked Loops (PLL) generate all  
clocks from single 32.768 kHz crystal input  
– Supports CPU System Management Mode  
(SMM)  
n Bus configurations  
– Multiple operating modes: High Speed PLL, Low  
Speed PLL, Doze, Sleep, Suspend, and Off. Fully  
static design allows stopped clock.  
– 16-bit data path  
– Optional bus configurations:  
— 386 Local Bus mode with subset ISA  
— Maximum ISA Bus mode  
– Four programmable chip selects  
– Built-in 8042 chip select  
– Comprehensive control of system and peripheral  
clocks  
– Five external power management control pins  
– Suspend refresh of DRAM array  
– Clock switching during ISA cycles  
n Serial port controller (16450 UART compatible)  
n Bidirectional parallel port (EPP compliant)  
– Low power consumption: 0.12 mW typical  
Suspend mode power  
– Simultaneous multiple-voltage I/O pads operate  
at either 3.3 V or 5 V. Core operates at 3.3 V for  
minimum power consumption.  
Publication# 20668 Rev: B Amendment/0  
Issue Date: October 1997  
This document contains information on a product under development at Advanced Micro Devices. The information  
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product  
without notice.  
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