PRELIMINARY
Élan™SC300
Highly Integrated, Low-Power, 32-Bit Microcontroller
– Zero wait-state access with 70 ns, Page mode
DISTINCTIVE CHARACTERISTICS
DRAMs
n Highly integrated, single-chip CPU and system
– Supports up to 16 Mbyte system memory
logic
– Supports up to 16 Mbyte of application ROM/
Flash, and 320 Kbyte direct ROM BIOS access.
Also supports shadow RAM
– Optimized for embedded PC applications
– Combines 32 bit, x86 compatible, low-voltage
CPU with memory controller, PC/AT peripheral
controllers, real-time clock, and PLL clock gener-
ators
– Fully PC/AT compatible
n Integrated PC/AT-compatible peripheral logic
– 0.7 micron, low-voltage, CMOS process, fully
static
– One programmable interval timer (fully 8254
compatible)
®
n Enhanced Am386 SXLV CPU core
– Two programmable interrupt controllers (8259A
compatible)
– 25 MHz or 33 MHz operating frequencies
– 3.3 V core, 3.3 V or 5 V memory and I/O
– Low-power, fully static design for long battery life
– Two DMA controllers (8237A compatible)
– Built-in real-time clock (146818A compatible),
with an additional 114 bytes of RAM
– System Management Mode (SMM) for power
management control
– Internal Phase-Locked Loops (PLL) generate all
clocks from single 32.768 kHz crystal input
n
Integrated power management functions
n Bus configurations
– Internal clock generators (using multiple Phase-
Locked Loops and one external 32-KHz crystal)
– 16-bit data path
– Optional bus configurations:
— Internal LCD controller with subset ISA
— 386 Local Bus mode with subset ISA
— Maximum ISA Bus mode
– Supports CPU System Management Mode
(SMM)
– Multiple operating modes: High Speed PLL, Low
Speed PLL, Doze, Sleep, Suspend, and Off. Fully
static design allows stopped clock.
– Four programmable chip selects
– Comprehensive control of system and peripheral
clocks
– Built-in 8042 chip select
n Serial port controller (16450 UART compatible)
n Bidirectional parallel port with EPP
n Integrates two PCMCIA Version 2.1 slots
n Integrated CGA-compatible LCD controller
– Fully 6845 compatible
– Five external power management control pins
– Suspend refresh of DRAM array
– Clock switching during ISA cycles
– Low power consumption: 0.12 mW typical
Suspend mode power
– 16 gray levels in Text mode; 2 or 4 levels in
Graphics mode
– Simultaneous multiple-voltage I/O pads operate
at either 3.3 V or 5 V. Core operates at 3.3 V for
minimum power consumption.
– Supports the following LCD Panel Sizes:
— 320 x 240 single scan (2 bpp)
n Integrated memory controller
– Controls symmetrically addressable DRAM or
asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit
DRAM or SRAM as main memory
— 640 x 200 single/dual scan (1 bpp)
— 480 x 320 single scan (1 bpp)
Publication# 18514 Rev: D Amendment/0
Issue Date: October 1997
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product
without notice.