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ELANSC300-25KI PDF预览

ELANSC300-25KI

更新时间: 2024-01-23 07:12:37
品牌 Logo 应用领域
超微 - AMD 微控制器外围集成电路时钟
页数 文件大小 规格书
139页 1344K
描述
Highly Integrated, Low-Power, 32-Bit Microcontroller

ELANSC300-25KI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP208,1.2SQ,20
针数:208Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.88
Is Samacsys:N具有ADC:NO
地址总线宽度:24位大小:32
最大时钟频率:14.336 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:16
JESD-30 代码:S-PQFP-G208JESD-609代码:e0
长度:28 mmI/O 线路数量:
端子数量:208最高工作温度:70 °C
最低工作温度:PWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V认证状态:Not Qualified
座面最大高度:1.6 mm速度:25 MHz
子类别:Microprocessors最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:28 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

ELANSC300-25KI 数据手册

 浏览型号ELANSC300-25KI的Datasheet PDF文件第2页浏览型号ELANSC300-25KI的Datasheet PDF文件第3页浏览型号ELANSC300-25KI的Datasheet PDF文件第4页浏览型号ELANSC300-25KI的Datasheet PDF文件第5页浏览型号ELANSC300-25KI的Datasheet PDF文件第6页浏览型号ELANSC300-25KI的Datasheet PDF文件第7页 
PRELIMINARY  
ÉlanSC300  
Highly Integrated, Low-Power, 32-Bit Microcontroller  
– Zero wait-state access with 70 ns, Page mode  
DISTINCTIVE CHARACTERISTICS  
DRAMs  
n Highly integrated, single-chip CPU and system  
– Supports up to 16 Mbyte system memory  
logic  
– Supports up to 16 Mbyte of application ROM/  
Flash, and 320 Kbyte direct ROM BIOS access.  
Also supports shadow RAM  
– Optimized for embedded PC applications  
– Combines 32 bit, x86 compatible, low-voltage  
CPU with memory controller, PC/AT peripheral  
controllers, real-time clock, and PLL clock gener-  
ators  
– Fully PC/AT compatible  
n Integrated PC/AT-compatible peripheral logic  
– 0.7 micron, low-voltage, CMOS process, fully  
static  
– One programmable interval timer (fully 8254  
compatible)  
®
n Enhanced Am386 SXLV CPU core  
– Two programmable interrupt controllers (8259A  
compatible)  
– 25 MHz or 33 MHz operating frequencies  
– 3.3 V core, 3.3 V or 5 V memory and I/O  
– Low-power, fully static design for long battery life  
– Two DMA controllers (8237A compatible)  
– Built-in real-time clock (146818A compatible),  
with an additional 114 bytes of RAM  
– System Management Mode (SMM) for power  
management control  
– Internal Phase-Locked Loops (PLL) generate all  
clocks from single 32.768 kHz crystal input  
n
Integrated power management functions  
n Bus configurations  
– Internal clock generators (using multiple Phase-  
Locked Loops and one external 32-KHz crystal)  
– 16-bit data path  
– Optional bus configurations:  
— Internal LCD controller with subset ISA  
— 386 Local Bus mode with subset ISA  
— Maximum ISA Bus mode  
– Supports CPU System Management Mode  
(SMM)  
– Multiple operating modes: High Speed PLL, Low  
Speed PLL, Doze, Sleep, Suspend, and Off. Fully  
static design allows stopped clock.  
– Four programmable chip selects  
– Comprehensive control of system and peripheral  
clocks  
– Built-in 8042 chip select  
n Serial port controller (16450 UART compatible)  
n Bidirectional parallel port with EPP  
n Integrates two PCMCIA Version 2.1 slots  
n Integrated CGA-compatible LCD controller  
– Fully 6845 compatible  
– Five external power management control pins  
– Suspend refresh of DRAM array  
– Clock switching during ISA cycles  
– Low power consumption: 0.12 mW typical  
Suspend mode power  
– 16 gray levels in Text mode; 2 or 4 levels in  
Graphics mode  
– Simultaneous multiple-voltage I/O pads operate  
at either 3.3 V or 5 V. Core operates at 3.3 V for  
minimum power consumption.  
– Supports the following LCD Panel Sizes:  
— 320 x 240 single scan (2 bpp)  
n Integrated memory controller  
– Controls symmetrically addressable DRAM or  
asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit  
DRAM or SRAM as main memory  
— 640 x 200 single/dual scan (1 bpp)  
— 480 x 320 single scan (1 bpp)  
Publication# 18514 Rev: D Amendment/0  
Issue Date: October 1997  
This document contains information on a product under development at Advanced Micro Devices. The information  
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product  
without notice.  

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