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EL4584CS PDF预览

EL4584CS

更新时间: 2024-09-17 22:49:11
品牌 Logo 应用领域
ELANTEC 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
16页 277K
描述
Horizontal Genlock, 4 FSC

EL4584CS 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SO-16Reach Compliance Code:unknown
风险等级:5.74Is Samacsys:N
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:36 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
主时钟/晶体标称频率:36 MHz认证状态:Not Qualified
子类别:Other Microprocessor ICs标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

EL4584CS 数据手册

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EL4584C  
Horizontal Genlock, 4 F  
SC  
Features  
# 36 MHz, general purpose PLL  
General Description  
The EL4584C is a PLL (Phase Lock Loop) sub system, designed  
for video applications but also suitable for general purpose use  
up to 36 MHz. In a video application this device generates a  
TTL/CMOS compatible Pixel Clock (Clk Out) which is a multi-  
ple of the TV Horizontal scan rate, and phase locked to it.  
# 4 F based timing (use the  
SC  
EL4585 for 8 F  
)
SC  
# Compatible w/EL4583 Sync  
Separator  
# VCXO, Xtal, or LC tank  
oscillator  
The reference signal is a horizontal sync signal, TTL/CMOS  
format, which can be easily derived from an analog composite  
video signal with the EL4583 Sync Separator. An input signal  
to ‘‘coast’’ is provided for applications were periodic distur-  
bances are present in the reference video timing such as VTR  
head switching. The Lock detector output indicates correct lock.  
k
#
2 ns jitter (VCXO)  
# User controlled PLL capture and  
lock  
# Compatible with NTSC and PAL  
TV formats  
The divider ratio is four ratios for NTSC and four similar ratios  
for the PAL video timing standards, by external selection of  
three control pins. These four ratios have been selected for com-  
# 8 pre-programmed TV scan rate  
clock divisors  
mon video applications including 4 F , 3 F , 13.5 MHz  
SC  
SC  
(CCIR 601 format) and square picture elements used in some  
workstation graphics. To generate 8 F , 6 F , 27 MHz (CCIR  
# Selectable external divide for  
custom ratios  
SC  
SC  
# Single 5V, low current operation  
601 format) etc. use the EL4585, which includes an additional  
divide by 2 stage.  
Applications  
# Pixel Clock regeneration  
# Video compression engine  
(MPEG) clock generator  
For applications where these frequencies are inappropriate or  
for general purpose PLL applications the internal divider can be  
bypassed and an external divider chain used.  
# Video capture or digitization  
FREQUENCIES and DIVISORS  
# PIP (Picture in Picture) timing  
generator  
Function  
Divisor  
3Fsc  
CCIR 601  
Square  
4Fsc  
851  
864  
944  
1135  
# Text or graphics overlay timing  
PAL Fosc (MHz)  
13.301  
13.5  
14.75  
17.734  
Divisor  
682  
858  
780  
910  
Ordering Information  
NTSC Fosc (MHz)  
10.738  
13.5  
12.273  
14.318  
Ý
Part No. Temp. Range Package Outline  
CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL.  
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion.  
3Fsc numbers do not yield integer divisors.  
a
EL4584CN -40 C to 85 C 16-Pin DIP MDP0031  
§
a
EL4584CS -40 C to 85 C 16-Lead SO MDP0027  
§
§
§
For 6Fsc and 8Fsc clock frequencies, see  
EL4585 datasheet.  
Connection Diagram  
EL4584 SO, P-DIP Packages  
Demo Board  
A demo PCB is available for this  
product. Request ‘‘EL4584/5 Demo  
Board’’.  
458417  
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these  
Ý
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.  
4584C  
©
1994 Elantec, Inc.  

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