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EHB0010A1MA-7E-E PDF预览

EHB0010A1MA-7E-E

更新时间: 2024-11-12 20:08:31
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器内存集成电路
页数 文件大小 规格书
113页 901K
描述
Memory Circuit, Flash+SDRAM, 4MX16, CMOS, PBGA151, ROHS COMPLIANT, FBGA-151

EHB0010A1MA-7E-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:VFBGA, BGA151,15X16,25
针数:151Reach Compliance Code:unknown
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:70 nsJESD-30 代码:R-PBGA-B151
长度:12 mm内存密度:67108864 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
混合内存类型:FLASH+SDRAM功能数量:1
端子数量:151字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-20 °C
组织:4MX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA151,15X16,25
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8,3/3.3 V
认证状态:Not Qualified座面最大高度:0.8 mm
最大待机电流:0.01 A子类别:Other Memory ICs
最大压摆率:0.08 mA最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.4 mm
Base Number Matches:1

EHB0010A1MA-7E-E 数据手册

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DATA SHEET  
64Mb Flash Memory +  
512Mb DDR SDRAM MCP  
EHB0010A1MA  
Description  
DDR SDRAM Specifications  
The EHB0010A1MA is a MCP (Multi Chip Package);  
organized the SpansionTM 64M bits flash memory  
(S99PL064J0039) and the Elpida 512M bits DDR  
SDRAM in one package.  
Density: 512M bits  
Organization  
⎯ × 32 bits: 4M words × 32 bits × 4 banks  
Power supply:  
D-VDD, D-VDDQ = 1.8V +0.15V/–0.1V  
Each flash memory and DDR SDRAM device operates  
separately.  
Data rate: 266Mbps (max.)  
2KB page size  
Row address: A0 to A12  
Column address: A0 to A8  
Four internal banks for concurrent operation  
Interface: LVCMOS  
Burst lengths (BL): 2, 4, 8  
Burst type (BT):  
Sequential (2, 4, 8)  
Interleave (2, 4, 8)  
/CAS Latency (CL): 3  
Precharge: auto precharge option for each burst  
access  
Package: 151-ball FBGA  
Operating ambient temperature range  
TA =20°C to +85°C  
Flash Memory Specifications  
Density: 64M bits  
Organization  
⎯ × 16 bits: 4M words × 16 bits  
Power supply: F-VDD = 2.7V to 3.6V  
Access time  
Address access: 70ns (max.)  
Page access: 30ns (max.)  
Power supply current (for F-VDD at 10MHz)  
Read: 45mA (typ.)  
Driver strength: full/half/quarter  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period: 7.8μs  
Write: 15mA (typ.)  
Standby mode: 0.2μA (typ.)  
Program/erase: 17mA (typ.)  
Cycling endurance: 100k cycle/sector  
Data retention: 10 years  
FlexBank Architecture: four separate banks, with up  
to two simultaneous operations per device  
Bank A: 8 Mbit (4 Kw x 8 and 32 Kw x 15)  
Bank B: 24 Mbit (32 Kw x 48)  
Bank C: 24 Mbit (32 Kw x 48)  
Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)  
Secured Silicon Sector region  
Up to 128 words accessible through a command  
sequence  
Up to 64 factory-locked words  
Up to 64 customer-lockable words  
Both top and bottom boot blocks in one device  
Document No. E0950E30 (Ver. 3.0)  
Date Published February 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
©Elpida Memory, Inc. 2006-2007  

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