Datasheet > EH3500ETTS-16.700M

EH3500ETTS-16.700M

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
日蚀 - ECLIPTEK		石英晶振
页数	文件大小	规格书
10页	954K
描述
CMOS, Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)

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Ecliptek | EH35 Series Oscillator

http://www.ecliptek.com/oscillators/EH35/

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EH35 Series Oscillator

Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)

2011/65 +

168 SVHC

2015/863

Revision F 02/27/2015

Electrical Specifications

Nominal Frequency

1.000MHz to 155.520MHz

Some frequencies within this range may not be available.

Frequency Tolerance/Stability

(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency

Stability over the Operating Temperature Range, Supply Voltage

Change, Output Load Change, First Year Aging at 25°C, Shock, and

Vibration)

±100ppm Maximum

±50ppm Maximum

±25ppm Maximum

±20ppm Maximum

Aging at 25°C

±5ppm/year Maximum

Operating Temperature Range

0°C to +70°C

-40°C to +85°C

Supply Voltage

Input Current

5.0V

±10%

No Load

50mA Maximum

Output Voltage Logic High (V

)

= -16mA

2.4V

Minimum with TTL Load

Minimum with HCMOS Load

-0.4V

Output Voltage Logic Low (V

Duty Cycle

)

= +16mA

0.4V

0.5V

Maximum with TTL Load

Maximum with HCMOS Load

50 ±10(%) Measured at 1.4V

with TTL Load or at 50% of waveform

with HCMOS Load from 1MHz to 70MHz. Measured at 50% of

waveform above 70MHz.

50 ±5(%) Measured at 50% of waveform.

Rise Time/Fall Time

Load Drive Capability

Measured over 0.8V

waveform with HCMOS load.

6nSec Maximum from 1MHz to 70MHz

4nSec Maximum from 70.000001MHz to 155.520MHz

to 2.0V

with TTL load or from 20% to 80% of

10 TTL Load or 50pF HCMOS Load Maximum from 1MHz to 70MHz

5 TTL Load or 15pF HCMOS Load Maximum from 70.000001MHz to

155.520MHz

Output Logic Type

Pin 1 Connection

CMOS

Tri-State (Disabled Output: High Impedance)

Tri-State Input Voltage (Vih and Vil)

Absolute Clock Jitter

+2.2V

+0.8V

Minimum or No Connect to Enable Output

Maximum to Disable Output (High Impedance)

±250pSec Maximum, ±100pSec Typical

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