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EG-2001CA 106.2500M-PCZL3 PDF预览

EG-2001CA 106.2500M-PCZL3

更新时间: 2024-09-16 22:58:47
品牌 Logo 应用领域
爱普生 - EPSON /
页数 文件大小 规格书
2页 375K
描述
OSCILLATOR SO 106.25MHZ CMOS SMD

EG-2001CA 106.2500M-PCZL3 数据手册

 浏览型号EG-2001CA 106.2500M-PCZL3的Datasheet PDF文件第2页 
Crystal oscillator  
Product Number (please contact us)  
EG-2021CA: Q3807CA00xxxx00  
EG-2001CA: Q3801CA00xxxx00  
LOW-JITTER SAW OSCILLATOR (SPSO)  
OUTPUT : CMOS  
EG - 2021  
/
2001CA  
Frequency range  
Supply voltage  
:
:
62.5 MHz to 250 MHz  
2.5 V  EG-2021CA  
3.3 V  EG-2001CA  
CMOS  
Output  
:
:
Function  
Output enable (OE)  
External dimensions : 7.0 × 5.0 × 1.2 mm  
Actual size  
Very low jitter and low phase noise by SAW unit.  
EG-2021CA  
EG-2001CA  
Specifications (characteristics)  
Specifications  
EG-2021CA  
Item  
Symbol  
Conditions / Remarks  
EG-2001CA  
62.500 MHz to  
170.000MHz  
170.001MHz to  
250.000MHz  
106.250 MHz to  
170.000 MHz  
3.3 V0.3 V  
Output frequency range  
f0  
Please contact us about available frequencies.  
Storage as single product.  
Supply voltage  
Storage temperature  
VCC  
T_stg  
2.5 V0.125 V  
-40 C to +100 C  
P: 0 C to +70 C  
Operating temperature  
Frequency tolerance  
0 C to +70C  
T_use  
f_tol  
R: -5 C to +85 C  
G: 50 10-6  
Z: 50 10-6  
Y,H: 100 10-6  
50 mA Max.  
H: 100 10-6  
Current consumption  
Disable current  
Symmetry  
ICC  
I_dis  
SYM  
VOH  
VOL  
25 mA Max.  
600 A Max.  
45 % to 55 % 40 % to 60 %  
30 mA Max.  
OE=VCC, No load condition  
OE=GND  
50 % VCC level, L_CMOSMax.  
IOH = -8 mA  
10 A Max.  
45 % to 55 %  
VCC-0.4 V Min.  
0.4 V Max.  
VCC-0.35 V Min.  
0.35 V Max.  
Output voltage  
IOL = 8 mA  
Output load condition (CMOS)  
Input voltage  
L_CMOS  
VIH  
VIL  
tr / tf  
t_str  
tDJ  
15 pF Max.  
70 % VCC Min.  
30 % VCC Max.  
2 ns Max.  
10 ms Max.  
0.2 ps Typ.  
3 ps Typ.  
OE terminal  
Rise time / Fall time  
Start-up time  
Between 20% VCC and80% VCC level, L_CMOSMax.  
Time at minimum supply voltage to be 0 s  
Deterministic Jitter  
tRJ  
Random Jitter  
Jitter *1  
tRMS  
tp-p  
tacc  
3 ps Typ.  
25 ps Typ.  
4 ps Typ.  
(RMS of total distribution)  
Peak to Peak  
Accumulated Jitter() n=2 to 50000 cycles  
Phase Jitter  
tPJ  
1 ps Max.  
Offset frequency: 12 kHz to 20 MHz  
Frequency aging  
f_aging  
10 10-6 / year Max.  
5 10-6 / year Max. +25 C, First year, VCC=2.5 V,3.3 V  
*1 Tested using a DTS-2075 Digital timing system made by WAVECREST with jitter analysis software VISI6.  
Product Name  
(Standard form)  
EG-2021 CA 125.000000MHz C H P A (⑤⑥⑦: GPA, GRA are not available)  
④⑤⑥⑦  
Frequency tolerance  
Operating temp.  
Model  
Package type Frequency  
G
±50 × 10-6  
P
R
0 to +70°C  
-5 to +85°C  
Output(C:CMOS)  
Frequency tolerance Operating temperature  
H
±100 × 10-6  
⑦Frequency aging (A*2: Frequency tolerance include agingN*3: Frequency tolerance exclude aging)  
Supply voltage  
3.3 V Typ.  
Frequency tolerance / Operating temperature  
Product Name  
(Standard form)  
EG-2001 CA 125.000000MHz P C H  
±100 × 10-6 / 0 to +70°C  
±100 × 10-6 / 0 to +70°C  
±50 × 10-6 / 0 to +70°C  
C
H*2  
Y*3  
Z*4  
④⑤⑥  
Model  
Package type Frequency  
Symmetry (P: 50±5%) Supply voltage  
Frequency tolerance / Operating temperature  
*2 This includes initial frequency tolerance, temperature variation, supply voltage variation, load variation, reflow drift, and aging(+25 C,10 years).  
*3 This includes initial frequency tolerance, temperature variation, supply voltage variation, load variation, and reflow drift.(except aging)  
*4 This includes initial frequency tolerance, and temperature variation.(except reflow drift, supply voltage variation, load variation and aging)  
External dimensions  
(Unit:mm)  
Footprint (Recommended) (Unit:mm)  
EG-2021CA  
EG-2001CA  
1.8  
1.4  
1.4  
#4  
#4  
#3  
#3  
#2  
#4  
#3  
#2  
E EG-2021  
125.000C  
HPA172A  
E 125.000H  
1PC124A  
7.0±0.2  
#1  
#2  
#1  
#1  
5.08  
7.0±0.2  
5.08  
Pin map  
Pin  
1
2
3
4
Pin map  
Pin. Connection  
Connection  
OE *1  
GND  
OUT  
VCC  
5.08  
1
2
3
4
OE *1  
GND  
OUT  
VCC  
5.08  
To maintain stable operation, provide a  
5.08  
0.01uF to 0.1uF by-pass capacitor at a  
location as near as possible to the  
power source terminal of the crystal  
product (between Vcc - GND).  
OE pin = HIGH : Specified frequency output.  
OE pin = LOW : Output is high impedance  
*1 Standby function built-in  
#2 is connected to the cover.  
*1 Standby function built-in  
#2 is connected to the cover.  

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