Datasheet > EDK1216CFBJ

EDK1216CFBJ

更新时间： 2024-09-15 06:55:55

品牌	Logo	应用领域
尔必达 - ELPIDA		双倍数据速率
页数	文件大小	规格书
56页	708K
描述
128M bits DDR Mobile RAM™

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中文翻译

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数据手册

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EDK1216CFBJ 数据手册

PRELIMINARY DATA SHEET

128M bits DDR Mobile RAM

EDK1216CFBJ (8M words × 16 bits)

Specifications

Pin Configurations

• Density: 128M bits

• Organization

/xxx indicates active low signal.

60-ball FBGA

2M words × 16 bits × 4 banks

• Package: 60-ball FBGA

Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.7V to 1.95V

• Clock frequency: 133MHz (max.)

• 1KB page size

VSS DQ15 VSSQ

VDDQ DQ13 DQ14

VSSQ DQ11 DQ12

VDDQ DQ9 DQ10

VSSQ UDQS DQ8

VDDQ DQ0

VDD

DQ1

DQ3

DQ5

DQ2 VSSQ

DQ4 VDDQ

DQ6 VSSQ

Row address: A0 to A11

Column address: A0 to A8

• Four internal banks for concurrent operation

• Interface: LVCMOS

DQ7 LDQS VDDQ

• Burst lengths (BL): 2, 4, 8, 16

• Burst type (BT):

Sequential (2, 4, 8, 16)

Interleave (2, 4, 8, 16)

• /CAS Latency (CL): 3

UDM

VSS

CKE

/CK

VDD

/WE

/CS

LDM

/CAS /RAS

BA1

A11

BA0

• Precharge: auto precharge option for each burst

A10

access

VSS

VDD

• Driver strength: normal, 1/2, 1/4, 1/8

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 4096 cycles/64ms

Average refresh period: 15.6µs

• Operating ambient temperature range

TA =−25°C to +85°C

(Top View)

Address input

A0 to A11

BA0, BA1

DQ0 to DQ15

UDQS, LDQS

/CS

Bank select address

Data-input/output

Input and output data strobe

Chip select

/RAS

/CAS

/WE

UDM, LDM

/CK

CKE

VDD

Row address strobe

Column address strobe

Write enable

Write data mask

Clock input

Features

• Low power consumption

• Partial Array Self-Refresh (PASR)

Differential clock input

Clock enable

• Auto Temperature Compensated Self-Refresh

(ATCSR) by built-in temperature sensor

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

VSS

• Double-data-rate architecture; two data transfers per

VDDQ

VSSQ

one clock cycle

• Bi-directional data strobe (DQS) is transmitted

/received with data for capturing data at the receiver.

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Burst termination by burst stop command and

Precharge command

Document No. E1194E20 (Ver. 2.0)

Date Published October 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2007-2009

12 3 4 5 6 7...56

中文翻译

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与EDK1216CFBJ相关器件

型号	品牌	获取价格	描述	数据表
EDK1216CFBJ-75-F	ELPIDA	获取价格	128M bits DDR Mobile RAM™
EDK156M010A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK157M016A9HAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK224M050A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK225M025A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK225M035A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK225M050A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK226M004A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK226M010A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK226M016A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General

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