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EDJ1116BABG-AG-E PDF预览

EDJ1116BABG-AG-E

更新时间: 2024-11-28 06:55:55
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
148页 1878K
描述
1G bits DDR3 SDRAM

EDJ1116BABG-AG-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA96,9X16,32
针数:96Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.84Is Samacsys:N
访问模式:MULTI BANK PAGE BURST最长访问时间:0.3 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):533 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B96JESD-609代码:e1
长度:13.5 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:96字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:64MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA96,9X16,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.5 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:4,8
最大待机电流:0.013 A子类别:DRAMs
最大压摆率:0.33 mA最大供电电压 (Vsup):1.575 V
最小供电电压 (Vsup):1.425 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.6 mm
Base Number Matches:1

EDJ1116BABG-AG-E 数据手册

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DATA SHEET  
1G bits DDR3 SDRAM  
EDJ1108BABG (128M words × 8 bits)  
EDJ1116BABG (64M words × 16 bits)  
Features  
Specifications  
Density: 1G bits  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 8 bits  
16M words × 8 bits × 8 banks (EDJ1108BABG)  
8M words × 16 bits × 8 banks (EDJ1116BABG)  
Package  
78-ball FBGA (EDJ1108BABG)  
96-ball FBGA (EDJ1116BABG)  
Lead-free (RoHS compliant)  
Power supply: VDD, VDDQ = 1.5V ± 0.075V  
Data rate  
1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)  
1KB page size (EDJ1108BABG)  
Row address: A0 to A13  
Column address: A0 to A9  
2KB page size (EDJ1116BABG)  
Row address: A0 to A12  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_15  
Burst lengths (BL): 8 and 4 with Burst Chop (BC)  
Burst type (BT):  
Sequential (8, 4 with BC)  
Interleave (8, 4 with BC)  
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11  
/CAS Write Latency (CWL): 5, 6, 7, 8  
prefetch pipelined architecture  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
On-Die Termination (ODT) for better signal quality  
Synchronous ODT  
Dynamic ODT  
Asynchronous ODT  
Multi Purpose Register (MPR) for temperature read  
out  
ZQ calibration for DQ drive and ODT  
Programmable Partial Array Self-Refresh (PASR)  
/RESET pin for Power-up sequence and reset  
function  
Precharge: auto precharge option for each burst  
SRT range:  
access  
Normal/extended  
Auto/manual self-refresh  
Programmable Output driver impedance control  
Driver strength: RZQ/7, RZQ/6 (RZQ = 240)  
Refresh: auto-refresh, self-refresh  
Refresh cycles  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1248E40 (Ver. 4.0)  
Date Published April 2009 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2007-2009  

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